3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_X86 1 /* This is a X86 CPU */
37 #define CONFIG_SC520 1 /* Include support for AMD SC520 */
38 #define CONFIG_ALI152X 1 /* Include support for Ali 152x SIO */
40 #define CFG_SDRAM_PRECHARGE_DELAY 6 /* 6T */
41 #define CFG_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
42 #define CFG_SDRAM_RAS_CAS_DELAY 3 /* 3T */
44 /* define at most one of these */
45 #undef CFG_SDRAM_CAS_LATENCY_2T
46 #define CFG_SDRAM_CAS_LATENCY_3T
48 #define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
49 #define CFG_RESET_GENERIC 1 /* use tripple-fault to reset cpu */
50 #undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */
51 #undef CFG_TIMER_SC520 /* use SC520 swtimers */
52 #define CFG_TIMER_GENERIC 1 /* use the i8254 PIT timers */
53 #undef CFG_TIMER_TSC /* use the Pentium TSC timers */
54 #define CFG_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
55 * in the SC520 on the CDP */
57 #define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */
59 #define CONFIG_SHOW_BOOT_PROGRESS 1
60 #define CONFIG_LAST_STAGE_INIT 1
63 * Size of malloc() pool
65 #define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
67 #define CONFIG_BAUDRATE 9600
70 * Command line configuration.
72 #include <config_cmd_default.h>
74 #define CONFIG_CMD_PCI
75 #define CONFIG_CMD_JFFS2
76 #define CONFIG_CMD_IDE
77 #define CONFIG_CMD_NET
78 #define CONFIG_CMD_EEPROM
80 #define CONFIG_BOOTDELAY 15
81 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
82 /* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
84 #if defined(CONFIG_CMD_KGDB)
85 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
86 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
90 * Miscellaneous configurable options
92 #define CFG_LONGHELP /* undef to save memory */
93 #define CFG_PROMPT "boot > " /* Monitor Command Prompt */
94 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
95 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
96 #define CFG_MAXARGS 16 /* max number of command args */
97 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
99 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
100 #define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
102 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
104 #define CFG_LOAD_ADDR 0x100000 /* default load address */
106 #define CFG_HZ 1024 /* incrementer freq: 1kHz */
108 /* valid baudrates */
109 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
111 /*-----------------------------------------------------------------------
112 * Physical Memory Map
114 #define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */
116 /*-----------------------------------------------------------------------
117 * FLASH and environment organization
119 #define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
120 #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
122 /* timeout values are in ticks */
123 #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
124 #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
126 #define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */
127 #define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */
129 /* allow to overwrite serial and ethaddr */
130 #define CONFIG_ENV_OVERWRITE
132 /* Environment in EEPROM */
133 #define CFG_ENV_IS_IN_EEPROM 1
135 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment EEPROM 16k is SPI is used or 128 bytes if MW is used*/
136 #define CFG_ENV_OFFSET 0
137 #define CONFIG_SC520_CDP_USE_SPI /* Store configuration in the SPI part */
138 #undef CONFIG_SC520_CDP_USE_MW /* Store configuration in the MicroWire part */
139 #define CONFIG_SPI_X 1
144 /* No command line, one static partition, whole device */
145 #undef CONFIG_JFFS2_CMDLINE
146 #define CONFIG_JFFS2_DEV "nor0"
147 #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
148 #define CONFIG_JFFS2_PART_OFFSET 0x00000000
150 /* mtdparts command line support */
152 #define CONFIG_JFFS2_CMDLINE
153 #define MTDIDS_DEFAULT "nor0=SC520CDP Flash Bank #0"
154 #define MTDPARTS_DEFAULT "mtdparts=SC520CDP Flash Bank #0:-(jffs2)"
157 /*-----------------------------------------------------------------------
160 #define CONFIG_NET_MULTI /* Multi ethernet cards support */
162 #define CONFIG_PCNET_79C973
163 #define CONFIG_PCNET_79C975
164 #define PCNET_HAS_PROM 1
166 /************************************************************
168 ************************************************************/
169 #define CFG_IDE_MAXBUS 1 /* max. 2 IDE busses */
170 #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
172 #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
173 /*#define CFG_ATA_IDE1_OFFSET 0x0170 /###* ide1 offset */
174 #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
175 #define CFG_ATA_REG_OFFSET 0 /* reg offset */
176 #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
177 #define CFG_ATA_BASE_ADDR 0
179 #undef CONFIG_IDE_LED /* no led for ide supported */
180 #undef CONFIG_IDE_RESET /* reset for ide unsupported... */
181 #undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
183 /************************************************************
185 ************************************************************/
186 #define CFG_SATA_SUPPORTED 1
187 #define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */
188 #define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */
189 #define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
190 #define CFG_ATA_PIIX 1 /*Supports ata_piix driver */
192 /************************************************************
193 * ATAPI support (experimental)
194 ************************************************************/
195 #define CONFIG_ATAPI /* enable ATAPI Support */
197 /************************************************************
198 * DISK Partition support
199 ************************************************************/
200 #define CONFIG_DOS_PARTITION
201 #define CONFIG_MAC_PARTITION
202 #define CONFIG_ISO_PARTITION /* Experimental */
204 /************************************************************
205 * Video/Keyboard support
206 ************************************************************/
207 #define CONFIG_VIDEO /* To enable video controller support */
208 #define CONFIG_I8042_KBD
211 /************************************************************
213 ***********************************************************/
214 #define CONFIG_RTC_MC146818
215 #undef CONFIG_WATCHDOG /* watchdog disabled */
220 #define CONFIG_PCI /* include pci support */
221 #define CONFIG_PCI_PNP /* pci plug-and-play */
222 #define CONFIG_PCI_SCAN_SHOW
224 #define CFG_FIRST_PCI_IRQ 10
225 #define CFG_SECOND_PCI_IRQ 9
226 #define CFG_THIRD_PCI_IRQ 11
227 #define CFG_FORTH_PCI_IRQ 15
229 #endif /* __CONFIG_H */