2 * Copyright (C) 2003 ETC s.r.o.
4 * SPDX-License-Identifier: GPL-2.0+
5 * Written by Peter Figuli <peposh@etc.sk>, 2003.
7 * 2003/13/06 Initial MP10 Support copied from wepep250
13 #define CONFIG_IMX 1 /* This is a Motorola MC9328MXL Chip */
14 #define CONFIG_SCB9328 1 /* on a scb9328tronix board */
16 #define CONFIG_IMX_SERIAL
17 #define CONFIG_IMX_SERIAL1
19 * Select serial console configuration
25 #define CONFIG_BOOTP_BOOTFILESIZE
26 #define CONFIG_BOOTP_BOOTPATH
27 #define CONFIG_BOOTP_GATEWAY
28 #define CONFIG_BOOTP_HOSTNAME
31 * Command line configuration.
33 #include <config_cmd_default.h>
35 #define CONFIG_CMD_PING
36 #define CONFIG_CMD_DHCP
38 #undef CONFIG_CMD_CONSOLE
39 #undef CONFIG_CMD_LOADS
40 #undef CONFIG_CMD_SOURCE
43 * Boot options. Setting delay to -1 stops autostart count down.
44 * NOTE: Sending parameters to kernel depends on kernel version and
45 * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept
46 * parameters at all! Do not get confused by them so.
48 #define CONFIG_BOOTDELAY -1
49 #define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328"
50 #define CONFIG_BOOTCOMMAND "bootm 10040000"
51 #define CONFIG_SHOW_BOOT_PROGRESS
52 #define CONFIG_NETMASK 255.255.255.0
53 #define CONFIG_IPADDR 10.10.10.9
54 #define CONFIG_SERVERIP 10.10.10.10
57 * General options for u-boot. Modify to save memory foot print
59 #define CONFIG_SYS_LONGHELP /* undef saves memory */
60 #define CONFIG_SYS_PROMPT "scb9328> " /* prompt string */
61 #define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
62 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
63 #define CONFIG_SYS_MAXARGS 16 /* max command args */
64 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
66 #define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
67 #define CONFIG_SYS_MEMTEST_END 0x08F00000
69 #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
71 #define CONFIG_BAUDRATE 115200
73 * Definitions related to passing arguments to kernel.
75 #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
76 #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
77 #define CONFIG_INITRD_TAG 1 /* send initrd params */
80 * Malloc pool need to host env + 128 Kb reserve for other allocations.
82 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
85 0x910a8300 Precharge Command CAS 3
86 0x910a8200 Precharge Command CAS 2
88 0xa10a8300 AutoRefresh Command CAS 3
89 0xa10a8200 Set AutoRefresh Command CAS 2 */
91 #define PRECHARGE_CMD 0x910a8200
92 #define AUTOREFRESH_CMD 0xa10a8200
98 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
99 #define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */
100 #define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */
102 #define CONFIG_SYS_TEXT_BASE 0x10000000
104 #define CONFIG_SYS_SDRAM_BASE SCB9328_SDRAM_1
105 #define CONFIG_SYS_INIT_SP_ADDR (SCB9328_SDRAM_1 + 0xf00000)
108 * Configuration for FLASH memory for the Synertronixx board
111 /* #define SCB9328_FLASH_32M */
114 #ifdef SCB9328_FLASH_32M
115 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
116 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
117 #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
118 #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
119 #define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */
120 #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
121 #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
122 #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
126 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
127 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */
128 #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
129 #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
130 #define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */
131 #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
132 #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */
133 #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */
134 #endif /* SCB9328_FLASH_32M */
136 /* This should be defined if CFI FLASH device is present. Actually benefit
137 is not so clear to me. In other words we can provide more informations
138 to user, but this expects more complex flash handling we do not provide
140 #undef CONFIG_SYS_FLASH_CFI
142 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* timeout for Erase operation */
143 #define CONFIG_SYS_FLASH_WRITE_TOUT 240000 /* timeout for Write operation */
145 #define CONFIG_SYS_FLASH_BASE SCB9328_FLASH_BASE
148 * This is setting for JFFS2 support in u-boot.
149 * Right now there is no gain for user, but later on booting kernel might be
150 * possible. Consider using XIP kernel running from flash to save RAM
152 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
154 #define CONFIG_SYS_JFFS2_FIRST_BANK 0
155 #define CONFIG_SYS_JFFS2_FIRST_SECTOR 5
156 #define CONFIG_SYS_JFFS2_NUM_BANKS 1
159 * Environment setup. Definitions of monitor location and size with
160 * definition of environment setup ends up in 2 possibilities.
161 * 1. Embeded environment - in u-boot code is space for environment
162 * 2. Environment is read from predefined sector of flash
163 * Right now we support 2. possiblity, but expecting no env placed
164 * on mentioned address right now. This also needs to provide whole
165 * sector for it - for us 256Kb is really waste of memory. U-boot uses
166 * default env. and until kernel parameters could be sent to kernel
167 * env. has no sense to us.
170 /* Setup for PA23 which is Reset Default PA23 but has to become
173 #define CONFIG_SYS_GPR_A_VAL 0x00800000
174 #define CONFIG_SYS_GIUS_A_VAL 0x0043fffe
176 #define CONFIG_SYS_MONITOR_BASE 0x10000000
177 #define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
178 #define CONFIG_ENV_IS_IN_FLASH 1
179 #define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
180 #define CONFIG_ENV_SIZE 0x20000
182 #define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
186 * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
187 * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
190 * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
191 * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
194 #define CONFIG_SYS_CS0U_VAL 0x000F2000
195 #define CONFIG_SYS_CS0L_VAL 0x11110d01
196 #define CONFIG_SYS_CS1U_VAL 0x000F0a00
197 #define CONFIG_SYS_CS1L_VAL 0x11110601
198 #define CONFIG_SYS_CS2U_VAL 0x0
199 #define CONFIG_SYS_CS2L_VAL 0x0
201 #define CONFIG_SYS_CS3U_VAL 0x000FFFFF
202 #define CONFIG_SYS_CS3L_VAL 0x00000303
204 #define CONFIG_SYS_CS4U_VAL 0x000F0a00
205 #define CONFIG_SYS_CS4L_VAL 0x11110301
208 #define CONFIG_SYS_CS5U_VAL 0x0000C210 */
210 /* #define CONFIG_SYS_CS5U_VAL 0x00008400
211 mal laenger mahcen, ob der bei 150MHz laenger haelt dann und
212 kaum langsamer ist */
213 /* #define CONFIG_SYS_CS5U_VAL 0x00009400
214 #define CONFIG_SYS_CS5L_VAL 0x11010D03 */
216 #define CONFIG_SYS_CS5U_VAL 0x00008400
217 #define CONFIG_SYS_CS5L_VAL 0x00000D03
219 #define CONFIG_DRIVER_DM9000 1
220 #define CONFIG_DM9000_BASE 0x16000000
221 #define DM9000_IO CONFIG_DM9000_BASE
222 #define DM9000_DATA (CONFIG_DM9000_BASE+4)
224 /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
227 0x002a141f: 191,9944MHz
234 0x08001800: 64MHz mit 16er Quarz
235 0x04001800: 96MHz mit 16er Quarz
236 0x04002400: 144MHz mit 16er Quarz
238 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
239 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
244 #define CONFIG_SYS_MPCTL0_VAL 0x00321431
246 #define CONFIG_SYS_MPCTL0_VAL 0x040e200e
253 #define CONFIG_SYS_SPCTL0_VAL 0x04002400
257 #define CONFIG_SYS_SPCTL0_VAL 0x04001800
261 #define CONFIG_SYS_SPCTL0_VAL 0x08001800
264 /* Das ist der BCLK Divider, der aus der System PLL
265 BCLK und HCLK erzeugt:
266 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0
267 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2
268 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2
269 0x2f001003 : 192MHz/5=38,4MHz
272 Bit 21: MPLL Restart */
275 #define CONFIG_SYS_CSCR_VAL 0x2f030003
279 #define CONFIG_SYS_CSCR_VAL 0x2f030403
283 * Well this has to be defined, but on the other hand it is used differently
284 * one may expect. For instance loadb command do not cares :-)
285 * So advice is - do not relay on this...
287 #define CONFIG_SYS_LOAD_ADDR 0x08400000
289 #define MHZ16QUARZINUSE
291 #ifdef MHZ16QUARZINUSE
292 #define CONFIG_SYSPLL_CLK_FREQ 16000000
294 #define CONFIG_SYSPLL_CLK_FREQ 16780000
297 #define CONFIG_SYS_CLK_FREQ 16780000
299 /* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */
300 #define CONFIG_SYS_FMCR_VAL 0x00000001
302 /* Bit[0:3] contain PERCLK1DIV for UART 1
303 0x000b00b ->b<- -> 192MHz/12=16MHz
304 0x000b00b ->8<- -> 144MHz/09=16MHz
305 0x000b00b ->3<- -> 64MHz/4=16MHz */
308 #define CONFIG_SYS_PCDR_VAL 0x000b00b5
312 #define CONFIG_SYS_PCDR_VAL 0x000b00b3
316 #define CONFIG_SYS_PCDR_VAL 0x000b00b8
319 #endif /* __CONFIG_H */