2 * Configuation settings for the sh7757lcr board
4 * Copyright (C) 2011 Renesas Solutions Corp.
6 * SPDX-License-Identifier: GPL-2.0+
12 #define CONFIG_CPU_SH7757 1
13 #define CONFIG_SH7757LCR_DDR_ECC 1
15 #define CONFIG_DISPLAY_BOARDINFO
16 #undef CONFIG_SHOW_BOOT_PROGRESS
19 #define SH7757LCR_SDRAM_BASE (0x80000000)
20 #define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
21 #define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
22 #define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
24 #define CONFIG_SYS_PBSIZE 256
25 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
28 #define CONFIG_CONS_SCIF2 1
30 #define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
31 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
33 #undef CONFIG_SYS_MEMTEST_SCRATCH
34 #undef CONFIG_SYS_LOADS_BAUD_CHANGE
36 #define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
37 #define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
38 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
39 (128 + 16) * 1024 * 1024)
41 #define CONFIG_SYS_MONITOR_BASE 0x00000000
42 #define CONFIG_SYS_MONITOR_LEN (256 * 1024)
43 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
44 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
47 #define CONFIG_SH_ETHER_USE_PORT 0
48 #define CONFIG_SH_ETHER_PHY_ADDR 1
49 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
50 #define CONFIG_BITBANGMII
51 #define CONFIG_BITBANGMII_MULTI
52 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
54 #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
55 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
56 #define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
57 #define SH7757LCR_ETHERNET_MAC_SIZE 17
58 #define SH7757LCR_ETHERNET_NUM_CH 2
61 #define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
64 #define CONFIG_SH_SPI_BASE 0xfe002000
67 #define CONFIG_SH_MMCIF 1
68 #define CONFIG_SH_MMCIF_ADDR 0xffcb0000
69 #define CONFIG_SH_MMCIF_CLK 48000000
72 #define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
73 #define SH7757LCR_GRA_OFFSET 0x1f000000
74 #define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
75 #define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
76 #define SH7757LCR_PCIEBRG_ADDR 0x00090000
77 #define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
80 #define CONFIG_ENV_IS_EMBEDDED
81 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
82 #define CONFIG_ENV_ADDR (0x00080000)
83 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
84 #define CONFIG_ENV_OVERWRITE 1
85 #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
86 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
87 #define CONFIG_EXTRA_ENV_SETTINGS \
88 "netboot=bootp; bootm\0"
91 #define CONFIG_SYS_CLK_FREQ 48000000
92 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
93 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
94 #define CONFIG_SYS_TMU_CLK_DIV 4
95 #endif /* __SH7757LCR_H */