3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 * Gary Jennejohn <gj@denx.de>
6 * David Mueller <d.mueller@elsoft.ch>
8 * Configuation settings for the SAMSUNG SMDK2410 board.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * High Level Configuration Options
36 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
37 #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
38 #define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
40 /* input clock of PLL */
41 #define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
44 #define USE_920T_MMU 1
45 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
48 * Size of malloc() pool
50 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
51 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
56 #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
57 #define CS8900_BASE 0x19000300
58 #define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
61 * select serial console configuration
63 #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
65 /************************************************************
67 ************************************************************/
68 #define CONFIG_RTC_S3C24X0 1
70 /* allow to overwrite serial and ethaddr */
71 #define CONFIG_ENV_OVERWRITE
73 #define CONFIG_BAUDRATE 115200
77 * Command line configuration.
79 #include <config_cmd_default.h>
81 #define CONFIG_CMD_CACHE
82 #define CONFIG_CMD_REGINFO
83 #define CONFIG_CMD_DATE
84 #define CONFIG_CMD_ELF
87 #define CONFIG_BOOTDELAY 3
88 /*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
89 /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
90 #define CONFIG_NETMASK 255.255.255.0
91 #define CONFIG_IPADDR 10.0.0.110
92 #define CONFIG_SERVERIP 10.0.0.1
93 /*#define CONFIG_BOOTFILE "elinos-lart" */
94 /*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
96 #if defined(CONFIG_CMD_KGDB)
97 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
98 /* what's this ? it's not used anywhere */
99 #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
103 * Miscellaneous configurable options
105 #define CFG_LONGHELP /* undef to save memory */
106 #define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */
107 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
108 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
109 #define CFG_MAXARGS 16 /* max number of command args */
110 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
112 #define CFG_MEMTEST_START 0x30000000 /* memtest works on */
113 #define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
115 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
117 #define CFG_LOAD_ADDR 0x33000000 /* default load address */
119 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
120 /* it to wrap 100 times (total 1562500) to get 1 sec. */
121 #define CFG_HZ 1562500
123 /* valid baudrates */
124 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
126 /*-----------------------------------------------------------------------
129 * The stack sizes are set up in start.S using the settings below
131 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
132 #ifdef CONFIG_USE_IRQ
133 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
134 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
137 /*-----------------------------------------------------------------------
138 * Physical Memory Map
140 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
141 #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
142 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
144 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
146 #define CFG_FLASH_BASE PHYS_FLASH_1
148 /*-----------------------------------------------------------------------
149 * FLASH and environment organization
152 #define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
154 #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
157 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
158 #ifdef CONFIG_AMD_LV800
159 #define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
160 #define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
161 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
163 #ifdef CONFIG_AMD_LV400
164 #define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
165 #define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
166 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
169 /* timeout values are in ticks */
170 #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
171 #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
173 #define CFG_ENV_IS_IN_FLASH 1
174 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
176 #endif /* __CONFIG_H */