git.sur5r.net Git - u-boot/blob - include/configs/socfpga_common.h

   1 /*
   2  * Copyright (C) 2012 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef __CONFIG_SOCFPGA_COMMON_H__
   7 #define __CONFIG_SOCFPGA_COMMON_H__
   8
   9 /* Virtual target or real hardware */
  10 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
  11
  12 #define CONFIG_SYS_THUMB_BUILD
  13
  14 /*
  15  * High level configuration
  16  */
  17 #define CONFIG_DISPLAY_BOARDINFO_LATE
  18 #define CONFIG_CLOCKS
  19
  20 #define CONFIG_CRC32_VERIFY
  21
  22 #define CONFIG_SYS_BOOTMAPSZ            (64 * 1024 * 1024)
  23
  24 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  25
  26 /* add target to build it automatically upon "make" */
  27 #define CONFIG_BUILD_TARGET             "u-boot-with-spl.sfp"
  28
  29 /*
  30  * Memory configurations
  31  */
  32 #define CONFIG_NR_DRAM_BANKS            1
  33 #define PHYS_SDRAM_1                    0x0
  34 #define CONFIG_SYS_MALLOC_LEN           (64 * 1024 * 1024)
  35 #define CONFIG_SYS_MEMTEST_START        PHYS_SDRAM_1
  36 #define CONFIG_SYS_MEMTEST_END          PHYS_SDRAM_1_SIZE
  37
  38 #define CONFIG_SYS_INIT_RAM_ADDR        0xFFFF0000
  39 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
  40 #define CONFIG_SYS_INIT_SP_OFFSET               \
  41         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  42 #define CONFIG_SYS_INIT_SP_ADDR                 \
  43         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  44
  45 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
  46 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
  47 #define CONFIG_SYS_TEXT_BASE            0x08000040
  48 #else
  49 #define CONFIG_SYS_TEXT_BASE            0x01000040
  50 #endif
  51
  52 /*
  53  * U-Boot general configurations
  54  */
  55 #define CONFIG_SYS_LONGHELP
  56 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
  57 #define CONFIG_SYS_PBSIZE       \
  58         (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  59                                                 /* Print buffer size */
  60 #define CONFIG_SYS_MAXARGS      32              /* Max number of command args */
  61 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
  62                                                 /* Boot argument buffer size */
  63 #define CONFIG_AUTO_COMPLETE                    /* Command auto complete */
  64 #define CONFIG_CMDLINE_EDITING                  /* Command history etc */
  65
  66 #ifndef CONFIG_SYS_HOSTNAME
  67 #define CONFIG_SYS_HOSTNAME     CONFIG_SYS_BOARD
  68 #endif
  69
  70 /*
  71  * Cache
  72  */
  73 #define CONFIG_SYS_L2_PL310
  74 #define CONFIG_SYS_PL310_BASE           SOCFPGA_MPUL2_ADDRESS
  75
  76 /*
  77  * SDRAM controller
  78  */
  79 #define CONFIG_ALTERA_SDRAM
  80
  81 /*
  82  * EPCS/EPCQx1 Serial Flash Controller
  83  */
  84 #ifdef CONFIG_ALTERA_SPI
  85 #define CONFIG_SF_DEFAULT_SPEED         30000000
  86 /*
  87  * The base address is configurable in QSys, each board must specify the
  88  * base address based on it's particular FPGA configuration. Please note
  89  * that the address here is incremented by  0x400  from the Base address
  90  * selected in QSys, since the SPI registers are at offset +0x400.
  91  * #define CONFIG_SYS_SPI_BASE          0xff240400
  92  */
  93 #endif
  94
  95 /*
  96  * Ethernet on SoC (EMAC)
  97  */
  98 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
  99 #define CONFIG_DW_ALTDESCRIPTOR
 100 #define CONFIG_MII
 101 #define CONFIG_AUTONEG_TIMEOUT          (15 * CONFIG_SYS_HZ)
 102 #define CONFIG_PHY_GIGE
 103 #endif
 104
 105 /*
 106  * FPGA Driver
 107  */
 108 #ifdef CONFIG_CMD_FPGA
 109 #define CONFIG_FPGA
 110 #define CONFIG_FPGA_ALTERA
 111 #define CONFIG_FPGA_SOCFPGA
 112 #define CONFIG_FPGA_COUNT               1
 113 #endif
 114
 115 /*
 116  * L4 OSC1 Timer 0
 117  */
 118 /* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 119 #define CONFIG_SYS_TIMERBASE            SOCFPGA_OSC1TIMER0_ADDRESS
 120 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 121 #define CONFIG_SYS_TIMER_COUNTER        (CONFIG_SYS_TIMERBASE + 0x4)
 122 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 123 #define CONFIG_SYS_TIMER_RATE           2400000
 124 #else
 125 #define CONFIG_SYS_TIMER_RATE           25000000
 126 #endif
 127
 128 /*
 129  * L4 Watchdog
 130  */
 131 #ifdef CONFIG_HW_WATCHDOG
 132 #define CONFIG_DESIGNWARE_WATCHDOG
 133 #define CONFIG_DW_WDT_BASE              SOCFPGA_L4WD0_ADDRESS
 134 #define CONFIG_DW_WDT_CLOCK_KHZ         25000
 135 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS   30000
 136 #endif
 137
 138 /*
 139  * MMC Driver
 140  */
 141 #ifdef CONFIG_CMD_MMC
 142 #define CONFIG_BOUNCE_BUFFER
 143 /* FIXME */
 144 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 145 #define CONFIG_SYS_MMC_MAX_BLK_COUNT    256     /* FIXME -- SPL only? */
 146 #endif
 147
 148 /*
 149  * NAND Support
 150  */
 151 #ifdef CONFIG_NAND_DENALI
 152 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 153 #define CONFIG_SYS_NAND_MAX_CHIPS       1
 154 #define CONFIG_SYS_NAND_ONFI_DETECTION
 155 #define CONFIG_NAND_DENALI_ECC_SIZE     512
 156 #define CONFIG_SYS_NAND_REGS_BASE       SOCFPGA_NANDREGS_ADDRESS
 157 #define CONFIG_SYS_NAND_DATA_BASE       SOCFPGA_NANDDATA_ADDRESS
 158 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 159 #endif
 160
 161 /*
 162  * I2C support
 163  */
 164 #define CONFIG_SYS_I2C
 165 #define CONFIG_SYS_I2C_BUS_MAX          4
 166 #define CONFIG_SYS_I2C_BASE             SOCFPGA_I2C0_ADDRESS
 167 #define CONFIG_SYS_I2C_BASE1            SOCFPGA_I2C1_ADDRESS
 168 #define CONFIG_SYS_I2C_BASE2            SOCFPGA_I2C2_ADDRESS
 169 #define CONFIG_SYS_I2C_BASE3            SOCFPGA_I2C3_ADDRESS
 170 /* Using standard mode which the speed up to 100Kb/s */
 171 #define CONFIG_SYS_I2C_SPEED            100000
 172 #define CONFIG_SYS_I2C_SPEED1           100000
 173 #define CONFIG_SYS_I2C_SPEED2           100000
 174 #define CONFIG_SYS_I2C_SPEED3           100000
 175 /* Address of device when used as slave */
 176 #define CONFIG_SYS_I2C_SLAVE            0x02
 177 #define CONFIG_SYS_I2C_SLAVE1           0x02
 178 #define CONFIG_SYS_I2C_SLAVE2           0x02
 179 #define CONFIG_SYS_I2C_SLAVE3           0x02
 180 #ifndef __ASSEMBLY__
 181 /* Clock supplied to I2C controller in unit of MHz */
 182 unsigned int cm_get_l4_sp_clk_hz(void);
 183 #define IC_CLK                          (cm_get_l4_sp_clk_hz() / 1000000)
 184 #endif
 185
 186 /*
 187  * QSPI support
 188  */
 189 /* Enable multiple SPI NOR flash manufacturers */
 190 #ifndef CONFIG_SPL_BUILD
 191 #define CONFIG_SPI_FLASH_MTD
 192 #define CONFIG_CMD_MTDPARTS
 193 #define CONFIG_MTD_DEVICE
 194 #define CONFIG_MTD_PARTITIONS
 195 #define MTDIDS_DEFAULT                  "nor0=ff705000.spi.0"
 196 #endif
 197 /* QSPI reference clock */
 198 #ifndef __ASSEMBLY__
 199 unsigned int cm_get_qspi_controller_clk_hz(void);
 200 #define CONFIG_CQSPI_REF_CLK            cm_get_qspi_controller_clk_hz()
 201 #endif
 202 #define CONFIG_CQSPI_DECODER            0
 203 #define CONFIG_BOUNCE_BUFFER
 204
 205 /*
 206  * Designware SPI support
 207  */
 208
 209 /*
 210  * Serial Driver
 211  */
 212 #define CONFIG_SYS_NS16550_SERIAL
 213 #define CONFIG_SYS_NS16550_REG_SIZE     -4
 214 #define CONFIG_SYS_NS16550_COM1         SOCFPGA_UART0_ADDRESS
 215 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 216 #define CONFIG_SYS_NS16550_CLK          1000000
 217 #else
 218 #define CONFIG_SYS_NS16550_CLK          100000000
 219 #endif
 220 #define CONFIG_CONS_INDEX               1
 221 #define CONFIG_BAUDRATE                 115200
 222
 223 /*
 224  * USB
 225  */
 226 #ifdef CONFIG_CMD_USB
 227 #define CONFIG_USB_DWC2
 228 #endif
 229
 230 /*
 231  * USB Gadget (DFU, UMS)
 232  */
 233 #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
 234 #define CONFIG_USB_FUNCTION_MASS_STORAGE
 235
 236 #define CONFIG_SYS_DFU_DATA_BUF_SIZE    (32 * 1024 * 1024)
 237 #define DFU_DEFAULT_POLL_TIMEOUT        300
 238
 239 /* USB IDs */
 240 #define CONFIG_G_DNL_UMS_VENDOR_NUM     0x0525
 241 #define CONFIG_G_DNL_UMS_PRODUCT_NUM    0xA4A5
 242 #endif
 243
 244 /*
 245  * U-Boot environment
 246  */
 247 #if !defined(CONFIG_ENV_SIZE)
 248 #define CONFIG_ENV_SIZE                 4096
 249 #endif
 250
 251 /* Environment for SDMMC boot */
 252 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
 253 #define CONFIG_SYS_MMC_ENV_DEV          0       /* device 0 */
 254 #define CONFIG_ENV_OFFSET               512     /* just after the MBR */
 255 #endif
 256
 257 /* Environment for QSPI boot */
 258 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
 259 #define CONFIG_ENV_OFFSET               0x00100000
 260 #define CONFIG_ENV_SECT_SIZE            (64 * 1024)
 261 #endif
 262
 263 /*
 264  * mtd partitioning for serial NOR flash
 265  *
 266  * device nor0 <ff705000.spi.0>, # parts = 6
 267  * #: name                size            offset          mask_flags
 268  * 0: u-boot              0x00100000      0x00000000      0
 269  * 1: env1                0x00040000      0x00100000      0
 270  * 2: env2                0x00040000      0x00140000      0
 271  * 3: UBI                 0x03e80000      0x00180000      0
 272  * 4: boot                0x00e80000      0x00180000      0
 273  * 5: rootfs              0x01000000      0x01000000      0
 274  *
 275  */
 276 #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT)
 277 #define MTDPARTS_DEFAULT        "mtdparts=ff705000.spi.0:"\
 278                                 "1m(u-boot),"           \
 279                                 "256k(env1),"           \
 280                                 "256k(env2),"           \
 281                                 "14848k(boot),"         \
 282                                 "16m(rootfs),"          \
 283                                 "-@1536k(UBI)\0"
 284 #endif
 285
 286 /* UBI and UBIFS support */
 287 #if defined(CONFIG_CMD_SF) || defined(CONFIG_CMD_NAND)
 288 #define CONFIG_CMD_UBIFS
 289 #define CONFIG_RBTREE
 290 #define CONFIG_LZO
 291 #endif
 292
 293 /*
 294  * SPL
 295  *
 296  * SRAM Memory layout:
 297  *
 298  * 0xFFFF_0000 ...... Start of SRAM
 299  * 0xFFFF_xxxx ...... Top of stack (grows down)
 300  * 0xFFFF_yyyy ...... Malloc area
 301  * 0xFFFF_zzzz ...... Global Data
 302  * 0xFFFF_FF00 ...... End of SRAM
 303  */
 304 #define CONFIG_SPL_FRAMEWORK
 305 #define CONFIG_SPL_TEXT_BASE            CONFIG_SYS_INIT_RAM_ADDR
 306 #define CONFIG_SPL_MAX_SIZE             (64 * 1024)
 307
 308 /* SPL SDMMC boot support */
 309 #ifdef CONFIG_SPL_MMC_SUPPORT
 310 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
 311 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      2
 312 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME         "u-boot-dtb.img"
 313 #endif
 314 #endif
 315
 316 /* SPL QSPI boot support */
 317 #ifdef CONFIG_SPL_SPI_SUPPORT
 318 #define CONFIG_SPL_SPI_LOAD
 319 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x40000
 320 #endif
 321
 322 /* SPL NAND boot support */
 323 #ifdef CONFIG_SPL_NAND_SUPPORT
 324 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 325 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 326 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x40000
 327 #endif
 328
 329 /*
 330  * Stack setup
 331  */
 332 #define CONFIG_SPL_STACK                CONFIG_SYS_INIT_SP_ADDR
 333
 334 #endif  /* __CONFIG_SOCFPGA_COMMON_H__ */