2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/socfpga_base_addrs.h>
10 #include "../../board/altera/socfpga/pinmux_config.h"
11 #include "../../board/altera/socfpga/iocsr_config.h"
12 #include "../../board/altera/socfpga/pll_config.h"
15 * High level configuration
17 /* Virtual target or real hardware */
18 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
21 #define CONFIG_SYS_DCACHE_OFF
24 #define CONFIG_MISC_INIT_R
25 #define CONFIG_SINGLE_BOOTLOADER
26 #define CONFIG_SOCFPGA
28 /* base address for .text section */
29 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
30 #define CONFIG_SYS_TEXT_BASE 0x08000040
32 #define CONFIG_SYS_TEXT_BASE 0x01000040
34 #define CONFIG_SYS_LOAD_ADDR 0x7fc0
36 /* Console I/O Buffer Size */
37 #define CONFIG_SYS_CBSIZE 256
38 /* Monitor Command Prompt */
39 #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
40 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
41 sizeof(CONFIG_SYS_PROMPT) + 16)
44 * Display CPU and Board Info
46 #define CONFIG_DISPLAY_CPUINFO
47 #define CONFIG_DISPLAY_BOARDINFO
50 * Enable early stage initialization at C environment
52 #define CONFIG_BOARD_EARLY_INIT_F
54 /* flat device tree */
55 #define CONFIG_OF_LIBFDT
56 /* skip updating the FDT blob */
57 #define CONFIG_FDT_BLOB_SKIP_UPDATE
58 /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
59 #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
61 #define CONFIG_SPL_RAM_DEVICE
62 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
63 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
64 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
67 * Memory allocation (MALLOC)
69 /* Room required on the stack for the environment data */
70 #define CONFIG_ENV_SIZE 1024
71 /* Size of DRAM reserved for malloc() use */
72 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
74 /* SP location before relocation, must use scratch RAM */
75 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
76 /* Reserving 0x100 space at back of scratch RAM for debug info */
77 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
78 /* Stack pointer prior relocation, must situated at on-chip RAM */
79 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
80 CONFIG_SYS_INIT_RAM_SIZE - \
81 GENERATED_GBL_DATA_SIZE)
85 * Command line configuration.
87 #define CONFIG_SYS_NO_FLASH
88 #include <config_cmd_default.h>
89 /* FAT file system support */
90 #define CONFIG_CMD_FAT
96 #define CONFIG_DOS_PARTITION 1
98 #ifdef CONFIG_SPL_BUILD
99 #undef CONFIG_PARTITIONS
106 /* Delay before automatically booting the default image */
107 #define CONFIG_BOOTDELAY 3
108 /* Enable auto completion of commands using TAB */
109 #define CONFIG_AUTO_COMPLETE
110 /* use "hush" command parser */
111 #define CONFIG_SYS_HUSH_PARSER
112 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
113 #define CONFIG_CMD_RUN
115 #define CONFIG_BOOTCOMMAND "run ramboot"
118 * arguments passed to the bootm command. The value of
119 * CONFIG_BOOTARGS goes into the environment value "bootargs".
120 * Do note the value will overide also the chosen node in FDT blob.
122 #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
124 #define CONFIG_EXTRA_ENV_SETTINGS \
126 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
127 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
128 "bootm ${loadaddr} - ${fdt_addr}\0" \
129 "bootimage=uImage\0" \
131 "fsloadcmd=ext2load\0" \
132 "bootm ${loadaddr} - ${fdt_addr}\0" \
133 "qspiroot=/dev/mtdblock0\0" \
134 "qspirootfstype=jffs2\0" \
135 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
136 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
137 "bootm ${loadaddr} - ${fdt_addr}\0"
139 /* using environment setting for stdin, stdout, stderr */
140 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
141 /* Enable the call to overwrite_console() */
142 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
143 /* Enable overwrite of previous console environment settings */
144 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
146 /* max number of command args */
147 #define CONFIG_SYS_MAXARGS 16
157 /* We have 1 bank of DRAM */
158 #define CONFIG_NR_DRAM_BANKS 1
160 #define CONFIG_SYS_SDRAM_BASE 0x00000000
161 /* SDRAM memory size */
162 #define PHYS_SDRAM_1_SIZE 0x40000000
164 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
165 #define CONFIG_SYS_MEMTEST_START 0x00000000
166 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
169 * NS16550 Configuration
171 #define UART0_BASE SOCFPGA_UART0_ADDRESS
172 #define CONFIG_SYS_NS16550
173 #define CONFIG_SYS_NS16550_SERIAL
174 #define CONFIG_SYS_NS16550_REG_SIZE -4
175 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
176 #define CONFIG_CONS_INDEX 1
177 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
178 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
179 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
180 #define V_NS16550_CLK 1000000
182 #define V_NS16550_CLK 100000000
184 #define CONFIG_BAUDRATE 115200
189 #define CONFIG_SYS_NO_FLASH
194 /* This timer use eosc1 where the clock frequency is fixed
195 * throughout any condition */
196 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
197 /* reload value when timer count to zero */
198 #define TIMER_LOAD_VAL 0xFFFFFFFF
200 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
201 #define CONFIG_SYS_TIMER_RATE 2400000
203 #define CONFIG_SYS_TIMER_RATE 25000000
205 #define CONFIG_SYS_TIMER_COUNTS_DOWN
206 #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
208 #define CONFIG_ENV_IS_NOWHERE
213 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
214 #define CONFIG_DESIGNWARE_ETH 1
217 #ifdef CONFIG_DESIGNWARE_ETH
218 #define CONFIG_EMAC0_BASE SOCFPGA_EMAC0_ADDRESS
219 #define CONFIG_EMAC1_BASE SOCFPGA_EMAC1_ADDRESS
220 /* console support for network */
221 #define CONFIG_CMD_DHCP
222 #define CONFIG_CMD_MII
223 #define CONFIG_CMD_NET
224 #define CONFIG_CMD_PING
226 #define CONFIG_NET_MULTI
227 #define CONFIG_DW_ALTDESCRIPTOR
228 #define CONFIG_DW_SEARCH_PHY
230 #define CONFIG_PHY_GIGE
231 #define CONFIG_DW_AUTONEG
232 #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ)
233 #define CONFIG_PHYLIB
234 #define CONFIG_PHY_MICREL
235 #define CONFIG_PHY_MICREL_KSZ9021
236 /* EMAC controller and PHY used */
237 #define CONFIG_EMAC_BASE CONFIG_EMAC1_BASE
238 #define CONFIG_EPHY_PHY_ADDR CONFIG_EPHY1_PHY_ADDR
239 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
240 #endif /* CONFIG_DESIGNWARE_ETH */
245 #define CONFIG_HW_WATCHDOG
246 #define CONFIG_HW_WATCHDOG_TIMEOUT_MS 2000
247 #define CONFIG_DESIGNWARE_WATCHDOG
248 #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
249 /* Clocks source frequency to watchdog timer */
250 #define CONFIG_DW_WDT_CLOCK_KHZ 25000
254 * SPL "Second Program Loader" aka Initial Software
257 /* Enable building of SPL globally */
258 #define CONFIG_SPL_FRAMEWORK
260 /* TEXT_BASE for linking the SPL binary */
261 #define CONFIG_SPL_TEXT_BASE 0xFFFF0000
263 /* Stack size for SPL */
264 #define CONFIG_SPL_STACK_SIZE (4 * 1024)
266 /* MALLOC size for SPL */
267 #define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
269 #define CONFIG_SPL_SERIAL_SUPPORT
270 #define CONFIG_SPL_BOARD_INIT
272 #define CHUNKSZ_CRC32 (1 * 1024)
274 #define CONFIG_CRC32_VERIFY
276 /* Linker script for SPL */
277 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
279 /* Support for common/libcommon.o in SPL binary */
280 #define CONFIG_SPL_LIBCOMMON_SUPPORT
281 /* Support for lib/libgeneric.o in SPL binary */
282 #define CONFIG_SPL_LIBGENERIC_SUPPORT
284 /* Support for watchdog */
285 #define CONFIG_SPL_WATCHDOG_SUPPORT
287 #endif /* __CONFIG_H */