2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/socfpga_base_addrs.h>
12 * High level configuration
17 #define CONFIG_SYS_DCACHE_OFF
20 #define CONFIG_MISC_INIT_R
21 #define CONFIG_SINGLE_BOOTLOADER
22 #define CONFIG_SOCFPGA
24 #define CONFIG_SYS_TEXT_BASE 0x08000040
25 #define V_NS16550_CLK 1000000
26 #define CONFIG_BAUDRATE 57600
27 #define CONFIG_SYS_HZ 1000
28 #define CONFIG_TIMER_CLOCK_KHZ 2400
29 #define CONFIG_SYS_LOAD_ADDR 0x7fc0
31 /* Console I/O Buffer Size */
32 #define CONFIG_SYS_CBSIZE 256
33 /* Monitor Command Prompt */
34 #define CONFIG_SYS_PROMPT "SOCFPGA_CYCLONE5 # "
35 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
36 sizeof(CONFIG_SYS_PROMPT) + 16)
39 * Display CPU and Board Info
41 #define CONFIG_DISPLAY_CPUINFO
42 #define CONFIG_DISPLAY_BOARDINFO
45 * Enable early stage initialization at C environment
47 #define CONFIG_BOARD_EARLY_INIT_F
49 /* flat device tree */
50 #define CONFIG_OF_LIBFDT
51 /* skip updating the FDT blob */
52 #define CONFIG_FDT_BLOB_SKIP_UPDATE
53 /* Initial Memory map size for Linux, minus 4k alignment for DFT blob */
54 #define CONFIG_SYS_BOOTMAPSZ ((256*1024*1024) - (4*1024))
56 #define CONFIG_SPL_RAM_DEVICE
57 #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
58 #define CONFIG_SYS_SPL_MALLOC_START ((unsigned long) (&__malloc_start))
59 #define CONFIG_SYS_SPL_MALLOC_SIZE (&__malloc_end - &__malloc_start)
62 * Memory allocation (MALLOC)
64 /* Room required on the stack for the environment data */
65 #define CONFIG_ENV_SIZE 1024
66 /* Size of DRAM reserved for malloc() use */
67 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
69 /* SP location before relocation, must use scratch RAM */
70 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
71 /* Reserving 0x100 space at back of scratch RAM for debug info */
72 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - 0x100)
73 /* Stack pointer prior relocation, must situated at on-chip RAM */
74 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
75 CONFIG_SYS_INIT_RAM_SIZE - \
76 GENERATED_GBL_DATA_SIZE)
80 * Command line configuration.
82 #define CONFIG_SYS_NO_FLASH
83 #include <config_cmd_default.h>
84 /* FAT file system support */
85 #define CONFIG_CMD_FAT
91 #define CONFIG_DOS_PARTITION 1
93 #ifdef CONFIG_SPL_BUILD
94 #undef CONFIG_PARTITIONS
101 /* Delay before automatically booting the default image */
102 #define CONFIG_BOOTDELAY 3
103 /* Enable auto completion of commands using TAB */
104 #define CONFIG_AUTO_COMPLETE
105 /* use "hush" command parser */
106 #define CONFIG_SYS_HUSH_PARSER
107 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
108 #define CONFIG_CMD_RUN
110 #define CONFIG_BOOTCOMMAND "run ramboot"
113 * arguments passed to the bootm command. The value of
114 * CONFIG_BOOTARGS goes into the environment value "bootargs".
115 * Do note the value will overide also the chosen node in FDT blob.
117 #define CONFIG_BOOTARGS "console=ttyS0,57600,mem=256M@0x0"
119 #define CONFIG_EXTRA_ENV_SETTINGS \
121 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
122 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
123 "bootm ${loadaddr} - ${fdt_addr}\0" \
124 "bootimage=uImage\0" \
126 "fsloadcmd=ext2load\0" \
127 "bootm ${loadaddr} - ${fdt_addr}\0" \
128 "qspiroot=/dev/mtdblock0\0" \
129 "qspirootfstype=jffs2\0" \
130 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
131 " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
132 "bootm ${loadaddr} - ${fdt_addr}\0"
134 /* using environment setting for stdin, stdout, stderr */
135 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
136 /* Enable the call to overwrite_console() */
137 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
138 /* Enable overwrite of previous console environment settings */
139 #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE
141 /* max number of command args */
142 #define CONFIG_SYS_MAXARGS 16
152 /* We have 1 bank of DRAM */
153 #define CONFIG_NR_DRAM_BANKS 1
155 #define CONFIG_SYS_SDRAM_BASE 0x00000000
156 /* SDRAM memory size */
157 #define PHYS_SDRAM_1_SIZE 0x80000000
159 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
160 #define CONFIG_SYS_MEMTEST_START 0x00000000
161 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
164 * NS16550 Configuration
166 #define UART0_BASE SOCFPGA_UART0_ADDRESS
167 #define CONFIG_SYS_NS16550
168 #define CONFIG_SYS_NS16550_SERIAL
169 #define CONFIG_SYS_NS16550_REG_SIZE -4
170 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
171 #define CONFIG_CONS_INDEX 1
172 #define CONFIG_SYS_NS16550_COM1 UART0_BASE
174 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
179 #define CONFIG_SYS_NO_FLASH
184 /* This timer use eosc1 where the clock frequency is fixed
185 * throughout any condition */
186 #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
188 /* reload value when timer count to zero */
189 #define TIMER_LOAD_VAL 0xFFFFFFFF
191 #define CONFIG_ENV_IS_NOWHERE
194 * SPL "Second Program Loader" aka Initial Software
197 /* Enable building of SPL globally */
199 #define CONFIG_SPL_FRAMEWORK
201 /* TEXT_BASE for linking the SPL binary */
202 #define CONFIG_SPL_TEXT_BASE 0xFFFF0000
204 /* Stack size for SPL */
205 #define CONFIG_SPL_STACK_SIZE (4 * 1024)
207 /* MALLOC size for SPL */
208 #define CONFIG_SPL_MALLOC_SIZE (5 * 1024)
210 #define CONFIG_SPL_SERIAL_SUPPORT
211 #define CONFIG_SPL_BOARD_INIT
213 #define CHUNKSZ_CRC32 (1 * 1024)
215 #define CONFIG_CRC32_VERIFY
217 /* Linker script for SPL */
218 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/socfpga/u-boot-spl.lds"
220 /* Support for common/libcommon.o in SPL binary */
221 #define CONFIG_SPL_LIBCOMMON_SUPPORT
222 /* Support for lib/libgeneric.o in SPL binary */
223 #define CONFIG_SPL_LIBGENERIC_SUPPORT
225 #endif /* __CONFIG_H */