2 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef __CONFIG_SOCFPGA_SR1500_H__
7 #define __CONFIG_SOCFPGA_SR1500_H__
9 #include <asm/arch/base_addr_ac5.h>
11 #define CONFIG_SYS_NO_FLASH
12 #define CONFIG_DOS_PARTITION
13 #define CONFIG_FAT_WRITE
15 #define CONFIG_HW_WATCHDOG
17 /* Memory configurations */
18 #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
21 #define CONFIG_BOOTFILE "uImage"
22 #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
23 #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
24 #define CONFIG_LOADADDR 0x01000000
25 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
27 /* Ethernet on SoC (EMAC) */
28 #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
29 /* The PHY is autodetected, so no MII PHY address is needed here */
30 #define CONFIG_PHY_MARVELL
31 #define PHY_ANEG_TIMEOUT 8000
33 #define CONFIG_EXTRA_ENV_SETTINGS \
35 "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
36 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
37 "bootm ${loadaddr} - ${fdt_addr}\0" \
38 "bootimage=zImage\0" \
40 "fdtimage=socfpga.dtb\0" \
41 "fsloadcmd=ext2load\0" \
42 "bootm ${loadaddr} - ${fdt_addr}\0" \
43 "mmcroot=/dev/mmcblk0p2\0" \
44 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
45 " root=${mmcroot} rw rootwait;" \
46 "bootz ${loadaddr} - ${fdt_addr}\0" \
47 "mmcload=mmc rescan;" \
48 "load mmc 0:1 ${loadaddr} ${bootimage};" \
49 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
50 "qspiload=sf probe && mtdparts default && run ubiload\0" \
51 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
52 " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
53 "bootz ${loadaddr} - ${fdt_addr}\0" \
54 "ubiload=ubi part UBI && ubifsmount ubi0 && " \
55 "ubifsload ${loadaddr} /boot/${bootimage} && " \
56 "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
59 #define CONFIG_ENV_IS_IN_SPI_FLASH
61 /* Enable SPI NOR flash reset, needed for SPI booting */
62 #define CONFIG_SPI_N25Q256A_RESET
67 #define CONFIG_BOOTCOUNT_LIMIT
68 /* last 2 lwords in OCRAM */
69 #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
70 #define CONFIG_SYS_BOOTCOUNT_BE
72 /* Environment setting for SPI flash */
73 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
74 #define CONFIG_ENV_SECT_SIZE (64 * 1024)
75 #define CONFIG_ENV_SIZE (16 * 1024)
76 #define CONFIG_ENV_OFFSET 0x000e0000
77 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
78 #define CONFIG_ENV_SPI_BUS 0
79 #define CONFIG_ENV_SPI_CS 0
80 #define CONFIG_ENV_SPI_MODE SPI_MODE_3
81 #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
82 #define CONFIG_SF_DEFAULT_SPEED 100000000
85 * The QSPI NOR flash layout on SR1500:
87 * 0000.0000 - 0003.ffff: SPL (4 times)
88 * 0004.0000 - 000d.ffff: U-Boot
89 * 000e.0000 - 000e.ffff: env1
90 * 000f.0000 - 000f.ffff: env2
93 /* The rest of the configuration is shared */
94 #include <configs/socfpga_common.h>
96 #endif /* __CONFIG_SOCFPGA_SR1500_H__ */