3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
31 #define CONFIG_MPC8220 1
32 #define CONFIG_SORCERY 1 /* Sorcery board */
34 /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
35 determine the CPU speed. */
36 #define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
37 #define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
39 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
40 #define BOOTFLAG_WARM 0x02 /* Software reboot */
43 * Serial console configuration
45 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
47 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
52 #define CONFIG_PCI_PNP 1
54 #define CONFIG_PCI_MEM_BUS 0x80000000
55 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
56 #define CONFIG_PCI_MEM_SIZE 0x10000000
58 #define CONFIG_PCI_IO_BUS 0x71000000
59 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
60 #define CONFIG_PCI_IO_SIZE 0x01000000
62 #define CONFIG_PCI_CFG_BUS 0x70000000
63 #define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
64 #define CONFIG_PCI_CFG_SIZE 0x01000000
68 * Command line configuration.
70 #include <config_cmd_default.h>
72 #define CONFIG_CMD_BOOTD
73 #define CONFIG_CMD_CACHE
74 #define CONFIG_CMD_DHCP
75 #define CONFIG_CMD_DIAG
76 #define CONFIG_CMD_ELF
77 #define CONFIG_CMD_I2C
78 #define CONFIG_CMD_NET
79 #define CONFIG_CMD_NFS
80 #define CONFIG_CMD_PCI
81 #define CONFIG_CMD_PING
82 #define CONFIG_CMD_REGINFO
83 #define CONFIG_CMD_SDRAM
84 #define CONFIG_CMD_SNTP
90 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
91 #define CONFIG_HOSTNAME sorcery
93 #define CONFIG_PREBOOT "echo;" \
94 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
97 #undef CONFIG_BOOTARGS
99 #define CONFIG_EXTRA_ENV_SETTINGS \
101 "nfsargs=setenv bootargs root=/dev/nfs rw " \
102 "nfsroot=$serverip:$rootpath\0" \
103 "ramargs=setenv bootargs root=/dev/ram rw\0" \
104 "addip=setenv bootargs $bootargs " \
105 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
106 ":$hostname:$netdev:off panic=1\0" \
107 "flash_nfs=run nfsargs addip;" \
108 "bootm $kernel_addr\0" \
109 "flash_self=run ramargs addip;" \
110 "bootm $kernel_addr $ramdisk_addr\0" \
111 "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
112 "rootpath=/opt/eldk/ppc_82xx\0" \
113 "bootfile=/tftpboot/sorcery/uImage\0" \
114 "kernel_addr=FFE00000\0" \
115 "ramdisk_addr=FFB00000\0" \
117 #define CONFIG_BOOTCOMMAND "run flash_self"
119 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
121 #define CONFIG_NET_MULTI
122 #define CONFIG_EEPRO100
127 #define CONFIG_HARD_I2C 1
128 #define CFG_I2C_MODULE 1
129 #define CFG_I2C_SPEED 100000 /* 100 kHz */
130 #define CFG_I2C_SLAVE 0x7F
132 /* Use the HUSH parser */
133 #define CFG_HUSH_PARSER
134 #ifdef CFG_HUSH_PARSER
135 #define CFG_PROMPT_HUSH_PS2 "> "
139 * Flexbus Chipselect configuration
140 * Beware: Some CS# seem to be mandatory (if these CS# are not set,
141 * board can hang-up in unpredictable place).
142 * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
146 #define CFG_CS0_BASE 0xf800
147 #define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */
148 #define CFG_CS0_CTRL 0x001019c0
151 #define CFG_CS1_BASE 0xf7e8
152 #define CFG_CS1_MASK 0x00040000 /* 256K */
153 #define CFG_CS1_CTRL 0x00101940 /* 8bit port size */
155 /* Atlas2 + Gemini */
156 #define CFG_CS2_BASE 0xf7e7
157 #define CFG_CS2_MASK 0x00010000 /* 64K*/
158 #define CFG_CS2_CTRL 0x001011c0 /* 16bit port size */
161 #define CFG_CS3_BASE 0xf7e6
162 #define CFG_CS3_MASK 0x00010000 /* 64K */
163 #define CFG_CS3_CTRL 0x00102140 /* 8Bit port size */
165 /* Foreign interface */
166 #define CFG_CS4_BASE 0xf7e5
167 #define CFG_CS4_MASK 0x00010000 /* 64K */
168 #define CFG_CS4_CTRL 0x00101dc0 /* 16bit port size */
171 #define CFG_CS5_BASE 0xf7e4
172 #define CFG_CS5_MASK 0x00010000 /* 64K */
173 #define CFG_CS5_CTRL 0x001000c0 /* 16bit port size */
175 #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
176 #define CFG_FLASH_BASE (CFG_FLASH0_BASE)
178 #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
179 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
181 #define CFG_FLASH_CFI_DRIVER
182 #define CFG_FLASH_CFI
183 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
184 CFG_FLASH_BASE+0x04000000 } /* two banks */
187 * Environment settings
189 #define CFG_ENV_IS_IN_FLASH 1
190 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000000 - 0x40000)
191 #define CFG_ENV_SIZE 0x4000 /* 16K */
192 #define CFG_ENV_SECT_SIZE 0x20000
193 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + 0x20000)
194 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
196 #define CONFIG_ENV_OVERWRITE 1
198 #if defined CFG_ENV_IS_IN_FLASH
199 #undef CFG_ENV_IS_IN_NVRAM
200 #undef CFG_ENV_IS_IN_EEPROM
201 #elif defined CFG_ENV_IS_IN_NVRAM
202 #undef CFG_ENV_IS_IN_FLASH
203 #undef CFG_ENV_IS_IN_EEPROM
204 #elif defined CFG_ENV_IS_IN_EEPROM
205 #undef CFG_ENV_IS_IN_NVRAM
206 #undef CFG_ENV_IS_IN_FLASH
212 #define CFG_MBAR 0xF0000000
213 #define CFG_SDRAM_BASE 0x00000000
214 #define CFG_DEFAULT_MBAR 0x80000000
215 #define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
216 #define CFG_SRAM_SIZE 0x8000
218 /* Use SRAM until RAM will be available */
219 #define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
220 #define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
222 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
223 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
224 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
226 #define CFG_MONITOR_BASE TEXT_BASE
227 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
228 # define CFG_RAMBOOT 1
231 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
232 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
233 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
235 /* SDRAM configuration (for SPD) */
236 #define CFG_SDRAM_TOTAL_BANKS 1
237 #define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
238 #define CFG_SDRAM_SPD_SIZE 0x100
239 #define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
241 /* SDRAM drive strength register (for SSTL_2 class II)*/
242 #define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
243 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
244 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
245 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
246 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
249 * Ethernet configuration
251 #define CONFIG_MPC8220_FEC 1
252 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
253 #define CONFIG_PHY_ADDR 0x1F
257 * Miscellaneous configurable options
259 #define CFG_LONGHELP /* undef to save memory */
260 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
261 #if defined(CONFIG_CMD_KGDB)
262 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
264 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
266 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
267 #define CFG_MAXARGS 16 /* max number of command args */
268 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
270 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
271 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
273 #define CFG_LOAD_ADDR 0x100000 /* default load address */
275 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
277 #define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
278 #if defined(CONFIG_CMD_KGDB)
279 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
283 * Various low-level settings
285 #define CFG_HID0_INIT 0
286 #define CFG_HID0_FINAL 0
289 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
290 #define CFG_HID0_FINAL HID0_ICE
293 #endif /* __CONFIG_H */