3 * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
31 #define CONFIG_MPC8220 1
32 #define CONFIG_SORCERY 1 /* Sorcery board */
34 #define CONFIG_SYS_TEXT_BASE 0xfff00000
36 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
38 /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to
39 determine the CPU speed. */
40 #define CONFIG_SYS_MPC8220_CLKIN 60000000 /* ... running at 60MHz */
41 #define CONFIG_SYS_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */
43 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
44 #define BOOTFLAG_WARM 0x02 /* Software reboot */
47 * Serial console configuration
49 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC */
51 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
52 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
56 #define CONFIG_PCI_PNP 1
58 #define CONFIG_PCI_MEM_BUS 0x80000000
59 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
60 #define CONFIG_PCI_MEM_SIZE 0x10000000
62 #define CONFIG_PCI_IO_BUS 0x71000000
63 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
64 #define CONFIG_PCI_IO_SIZE 0x01000000
66 #define CONFIG_PCI_CFG_BUS 0x70000000
67 #define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS
68 #define CONFIG_PCI_CFG_SIZE 0x01000000
74 #define CONFIG_BOOTP_BOOTFILESIZE
75 #define CONFIG_BOOTP_BOOTPATH
76 #define CONFIG_BOOTP_GATEWAY
77 #define CONFIG_BOOTP_HOSTNAME
81 * Command line configuration.
83 #include <config_cmd_default.h>
85 #define CONFIG_CMD_BOOTD
86 #define CONFIG_CMD_CACHE
87 #define CONFIG_CMD_DHCP
88 #define CONFIG_CMD_DIAG
89 #define CONFIG_CMD_ELF
90 #define CONFIG_CMD_I2C
91 #define CONFIG_CMD_NET
92 #define CONFIG_CMD_NFS
93 #define CONFIG_CMD_PCI
94 #define CONFIG_CMD_PING
95 #define CONFIG_CMD_REGINFO
96 #define CONFIG_CMD_SDRAM
97 #define CONFIG_CMD_SNTP
101 * Default Environment
103 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
104 #define CONFIG_HOSTNAME sorcery
106 #define CONFIG_PREBOOT "echo;" \
107 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
110 #undef CONFIG_BOOTARGS
112 #define CONFIG_EXTRA_ENV_SETTINGS \
114 "nfsargs=setenv bootargs root=/dev/nfs rw " \
115 "nfsroot=$serverip:$rootpath\0" \
116 "ramargs=setenv bootargs root=/dev/ram rw\0" \
117 "addip=setenv bootargs $bootargs " \
118 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
119 ":$hostname:$netdev:off panic=1\0" \
120 "flash_nfs=run nfsargs addip;" \
121 "bootm $kernel_addr\0" \
122 "flash_self=run ramargs addip;" \
123 "bootm $kernel_addr $ramdisk_addr\0" \
124 "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \
125 "rootpath=/opt/eldk/ppc_82xx\0" \
126 "bootfile=/tftpboot/sorcery/uImage\0" \
127 "kernel_addr=FFE00000\0" \
128 "ramdisk_addr=FFB00000\0" \
130 #define CONFIG_BOOTCOMMAND "run flash_self"
132 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
134 #define CONFIG_NET_MULTI
135 #define CONFIG_EEPRO100
140 #define CONFIG_HARD_I2C 1
141 #define CONFIG_SYS_I2C_MODULE 1
142 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
143 #define CONFIG_SYS_I2C_SLAVE 0x7F
145 /* Use the HUSH parser */
146 #define CONFIG_SYS_HUSH_PARSER
147 #ifdef CONFIG_SYS_HUSH_PARSER
148 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
152 * Flexbus Chipselect configuration
153 * Beware: Some CS# seem to be mandatory (if these CS# are not set,
154 * board can hang-up in unpredictable place).
155 * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
159 #define CONFIG_SYS_CS0_BASE 0xf800
160 #define CONFIG_SYS_CS0_MASK 0x08000000 /* 128 MB (two chips) */
161 #define CONFIG_SYS_CS0_CTRL 0x001019c0
164 #define CONFIG_SYS_CS1_BASE 0xf7e8
165 #define CONFIG_SYS_CS1_MASK 0x00040000 /* 256K */
166 #define CONFIG_SYS_CS1_CTRL 0x00101940 /* 8bit port size */
168 /* Atlas2 + Gemini */
169 #define CONFIG_SYS_CS2_BASE 0xf7e7
170 #define CONFIG_SYS_CS2_MASK 0x00010000 /* 64K*/
171 #define CONFIG_SYS_CS2_CTRL 0x001011c0 /* 16bit port size */
174 #define CONFIG_SYS_CS3_BASE 0xf7e6
175 #define CONFIG_SYS_CS3_MASK 0x00010000 /* 64K */
176 #define CONFIG_SYS_CS3_CTRL 0x00102140 /* 8Bit port size */
178 /* Foreign interface */
179 #define CONFIG_SYS_CS4_BASE 0xf7e5
180 #define CONFIG_SYS_CS4_MASK 0x00010000 /* 64K */
181 #define CONFIG_SYS_CS4_CTRL 0x00101dc0 /* 16bit port size */
184 #define CONFIG_SYS_CS5_BASE 0xf7e4
185 #define CONFIG_SYS_CS5_MASK 0x00010000 /* 64K */
186 #define CONFIG_SYS_CS5_CTRL 0x001000c0 /* 16bit port size */
188 #define CONFIG_SYS_FLASH0_BASE (CONFIG_SYS_CS0_BASE << 16)
189 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_FLASH0_BASE)
191 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
192 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
194 #define CONFIG_FLASH_CFI_DRIVER
195 #define CONFIG_SYS_FLASH_CFI
196 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
197 CONFIG_SYS_FLASH_BASE+0x04000000 } /* two banks */
200 * Environment settings
202 #define CONFIG_ENV_IS_IN_FLASH 1
203 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000000 - 0x40000)
204 #define CONFIG_ENV_SIZE 0x4000 /* 16K */
205 #define CONFIG_ENV_SECT_SIZE 0x20000
206 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + 0x20000)
207 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
209 #define CONFIG_ENV_OVERWRITE 1
211 #if defined CONFIG_ENV_IS_IN_FLASH
212 #undef CONFIG_ENV_IS_IN_NVRAM
213 #undef CONFIG_ENV_IS_IN_EEPROM
214 #elif defined CONFIG_ENV_IS_IN_NVRAM
215 #undef CONFIG_ENV_IS_IN_FLASH
216 #undef CONFIG_ENV_IS_IN_EEPROM
217 #elif defined CONFIG_ENV_IS_IN_EEPROM
218 #undef CONFIG_ENV_IS_IN_NVRAM
219 #undef CONFIG_ENV_IS_IN_FLASH
225 #define CONFIG_SYS_MBAR 0xF0000000
226 #define CONFIG_SYS_SDRAM_BASE 0x00000000
227 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
228 #define CONFIG_SYS_SRAM_BASE (CONFIG_SYS_MBAR + 0x20000)
229 #define CONFIG_SYS_SRAM_SIZE 0x8000
231 /* Use SRAM until RAM will be available */
232 #define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MBAR + 0x20000)
233 #define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
235 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
236 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
239 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
240 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
241 # define CONFIG_SYS_RAMBOOT 1
244 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
245 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
246 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
248 /* SDRAM configuration (for SPD) */
249 #define CONFIG_SYS_SDRAM_TOTAL_BANKS 1
250 #define CONFIG_SYS_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */
251 #define CONFIG_SYS_SDRAM_SPD_SIZE 0x100
252 #define CONFIG_SYS_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */
254 /* SDRAM drive strength register (for SSTL_2 class II)*/
255 #define CONFIG_SYS_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \
256 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
257 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \
258 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \
259 (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT))
262 * Ethernet configuration
264 #define CONFIG_MPC8220_FEC 1
265 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
266 #define CONFIG_PHY_ADDR 0x1F
270 * Miscellaneous configurable options
272 #define CONFIG_SYS_LONGHELP /* undef to save memory */
273 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
274 #if defined(CONFIG_CMD_KGDB)
275 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
277 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
279 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
280 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
281 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
283 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
284 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
286 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
288 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
290 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
291 #if defined(CONFIG_CMD_KGDB)
292 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
296 * Various low-level settings
298 #define CONFIG_SYS_HID0_INIT 0
299 #define CONFIG_SYS_HID0_FINAL 0
302 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
303 #define CONFIG_SYS_HID0_FINAL HID0_ICE
306 #endif /* __CONFIG_H */