2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * (C) Copyright 2004-2005
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * High Level Configuration Options
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37 #define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38 #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
39 #define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
40 #define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
42 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
44 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
45 #define BOOTFLAG_WARM 0x02 /* Software reboot */
48 * Serial console configuration
50 #define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
51 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
52 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
55 #undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */
56 #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
57 #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
58 #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
59 #define CONFIG_BOARD_EARLY_INIT_R
60 #endif /* CONFIG_STK52XX */
64 * 0x40000000 - 0x4fffffff - PCI Memory
65 * 0x50000000 - 0x50ffffff - PCI IO Space
69 #define CONFIG_PCI_PNP 1
70 /* #define CONFIG_PCI_SCAN_SHOW 1 */
72 #define CONFIG_PCI_MEM_BUS 0x40000000
73 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
74 #define CONFIG_PCI_MEM_SIZE 0x10000000
76 #define CONFIG_PCI_IO_BUS 0x50000000
77 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
78 #define CONFIG_PCI_IO_SIZE 0x01000000
80 #define CONFIG_NET_MULTI 1
81 #define CONFIG_EEPRO100 1
82 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
83 #define CONFIG_NS8382X 1
84 #endif /* CONFIG_STK52XX */
91 #define CONFIG_VIDEO_SM501
92 #define CONFIG_VIDEO_SM501_32BPP
93 #define CONFIG_CFB_CONSOLE
94 #define CONFIG_VIDEO_LOGO
95 #define CONFIG_VGA_AS_SINGLE_DEVICE
96 #define CONFIG_CONSOLE_EXTRA_INFO
97 #define CONFIG_VIDEO_SW_CURSOR
98 #define CONFIG_SPLASH_SCREEN
99 #define CFG_CONSOLE_IS_IN_ENV
103 #define CONFIG_MAC_PARTITION
104 #define CONFIG_DOS_PARTITION
105 #define CONFIG_ISO_PARTITION
108 #ifdef CONFIG_STK52XX
109 #define CONFIG_USB_OHCI
110 #define CONFIG_USB_STORAGE
114 #define CONFIG_POST (CFG_POST_MEMORY | \
119 /* preserve space for the post_word at end of on-chip SRAM */
120 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
127 #define CONFIG_BOOTP_BOOTFILESIZE
128 #define CONFIG_BOOTP_BOOTPATH
129 #define CONFIG_BOOTP_GATEWAY
130 #define CONFIG_BOOTP_HOSTNAME
134 * Command line configuration.
136 #include <config_cmd_default.h>
138 #define CONFIG_CMD_ASKENV
139 #define CONFIG_CMD_DATE
140 #define CONFIG_CMD_DHCP
141 #define CONFIG_CMD_ECHO
142 #define CONFIG_CMD_EEPROM
143 #define CONFIG_CMD_I2C
144 #define CONFIG_CMD_MII
145 #define CONFIG_CMD_NFS
146 #define CONFIG_CMD_PING
147 #define CONFIG_CMD_REGINFO
148 #define CONFIG_CMD_SNTP
150 #if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
151 #define CONFIG_CMD_IDE
152 #define CONFIG_CMD_FAT
153 #define CONFIG_CMD_EXT2
156 #ifdef CONFIG_STK52XX
157 #define CONFIG_CMD_USB
158 #define CONFIG_CMD_FAT
162 #define CONFIG_CMD_BMP
166 #define CONFIG_CMD_PCI
167 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
171 #define CONFIG_CMD_DIAG
175 #define CONFIG_TIMESTAMP /* display image timestamps */
177 #if (TEXT_BASE == 0xFC000000) /* Boot low */
178 # define CFG_LOWBOOT 1
184 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
186 #define CONFIG_PREBOOT "echo;" \
187 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
190 #undef CONFIG_BOOTARGS
192 #define CONFIG_EXTRA_ENV_SETTINGS \
194 "rootpath=/opt/eldk/ppc_6xx\0" \
195 "ramargs=setenv bootargs root=/dev/ram rw\0" \
196 "nfsargs=setenv bootargs root=/dev/nfs rw " \
197 "nfsroot=${serverip}:${rootpath}\0" \
198 "addip=setenv bootargs ${bootargs} " \
199 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
200 ":${hostname}:${netdev}:off panic=1\0" \
201 "flash_self=run ramargs addip;" \
202 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
203 "flash_nfs=run nfsargs addip;" \
204 "bootm ${kernel_addr}\0" \
205 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
206 "bootfile=/tftpboot/tqm5200/uImage\0" \
207 "load=tftp 200000 ${u-boot}\0" \
208 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
209 "update=protect off FC000000 FC05FFFF;" \
210 "erase FC000000 FC05FFFF;" \
211 "cp.b 200000 FC000000 ${filesize};" \
212 "protect on FC000000 FC05FFFF\0" \
215 #define CONFIG_BOOTCOMMAND "run net_nfs"
218 * IPB Bus clocking configuration.
220 #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
222 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
224 * PCI Bus clocking configuration
226 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
227 * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
228 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
230 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
236 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
237 #ifdef CONFIG_TQM5200_REV100
238 #define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
240 #define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
244 * I2C clock frequency
246 * Please notice, that the resulting clock frequency could differ from the
247 * configured value. This is because the I2C clock is derived from system
248 * clock over a frequency divider with only a few divider values. U-boot
249 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
250 * approximation allways lies below the configured value, never above.
252 #define CFG_I2C_SPEED 100000 /* 100 kHz */
253 #define CFG_I2C_SLAVE 0x7F
256 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
257 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
258 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
259 * same configuration could be used.
261 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
262 #define CFG_I2C_EEPROM_ADDR_LEN 2
263 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
264 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
267 * HW-Monitor configuration on Mini-FAP
269 #if defined (CONFIG_MINIFAP)
270 #define CFG_I2C_HWMON_ADDR 0x2C
273 /* List of I2C addresses to be verified by POST */
274 #if defined (CONFIG_MINIFAP)
276 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
277 CFG_I2C_HWMON_ADDR, \
282 * Flash configuration
284 #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
286 /* use CFI flash driver if no module variant is spezified */
287 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
288 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
289 #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
290 #define CFG_FLASH_EMPTY_INFO
291 #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
292 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
293 #undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
295 #if !defined(CFG_LOWBOOT)
296 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
297 #else /* CFG_LOWBOOT */
298 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
299 #endif /* CFG_LOWBOOT */
300 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
302 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
303 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
307 * Environment settings
309 #define CFG_ENV_IS_IN_FLASH 1
310 #define CFG_ENV_SIZE 0x10000
311 #define CFG_ENV_SECT_SIZE 0x20000
312 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
313 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
318 #define CFG_MBAR 0xF0000000
319 #define CFG_SDRAM_BASE 0x00000000
320 #define CFG_DEFAULT_MBAR 0x80000000
322 /* Use ON-Chip SRAM until RAM will be available */
323 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
325 /* preserve space for the post_word at end of on-chip SRAM */
326 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
328 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
332 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
333 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
334 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
336 #define CFG_MONITOR_BASE TEXT_BASE
337 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
338 # define CFG_RAMBOOT 1
341 #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
342 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
343 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
346 * Ethernet configuration
348 #define CONFIG_MPC5xxx_FEC 1
350 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
352 /* #define CONFIG_FEC_10MBIT 1 */
353 #define CONFIG_PHY_ADDR 0x00
358 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
359 * Bit 0 (mask: 0x80000000): 1
360 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
361 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
362 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
363 * Use for REV200 STK52XX boards. Do not use with REV100 modules
364 * (because, there I2C1 is used as I2C bus)
365 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
366 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
367 * 000 -> All PSC2 pins are GIOPs
368 * 001 -> CAN1/2 on PSC2 pins
369 * Use for REV100 STK52xx boards
372 * use as UART. Pins PSC6_0 to PSC6_3 are used.
373 * Bits 9:11 (mask: 0x00700000):
374 * 101 -> PSC6 : Extended POST test is not available
375 * on MINI-FAP and TQM5200_IB:
376 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
377 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
378 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
381 #if defined (CONFIG_MINIFAP)
382 # define CFG_GPS_PORT_CONFIG 0x91000004
383 #elif defined (CONFIG_STK52XX)
384 # if defined (CONFIG_STK52XX_REV100)
385 # define CFG_GPS_PORT_CONFIG 0x81500014
386 # else /* STK52xx REV200 and above */
387 # if defined (CONFIG_TQM5200_REV100)
388 # error TQM5200 REV100 not supported on STK52XX REV200 or above
389 # else/* TQM5200 REV200 and above */
390 # define CFG_GPS_PORT_CONFIG 0x91500004
393 #else /* TMQ5200 Inbetriebnahme-Board */
394 # define CFG_GPS_PORT_CONFIG 0x81000004
400 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
403 * Miscellaneous configurable options
405 #define CFG_LONGHELP /* undef to save memory */
406 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
407 #if defined(CONFIG_CMD_KGDB)
408 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
410 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
412 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
413 #define CFG_MAXARGS 16 /* max number of command args */
414 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
416 /* Enable an alternate, more extensive memory test */
417 #define CFG_ALT_MEMTEST
419 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
420 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
422 #define CFG_LOAD_ADDR 0x100000 /* default load address */
424 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
426 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
427 #if defined(CONFIG_CMD_KGDB)
428 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
432 * Enable loopw command.
437 * Various low-level settings
439 #if defined(CONFIG_MPC5200)
440 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
441 #define CFG_HID0_FINAL HID0_ICE
443 #define CFG_HID0_INIT 0
444 #define CFG_HID0_FINAL 0
447 #define CFG_BOOTCS_START CFG_FLASH_BASE
448 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
449 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
450 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
452 #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
454 #define CFG_CS0_START CFG_FLASH_BASE
455 #define CFG_CS0_SIZE CFG_FLASH_SIZE
457 #define CONFIG_LAST_STAGE_INIT
460 * SRAM - Do not map below 2 GB in address space, because this area is used
461 * for SDRAM autosizing.
463 #define CFG_CS2_START 0xE5000000
464 #define CFG_CS2_SIZE 0x100000 /* 1 MByte */
465 #define CFG_CS2_CFG 0x0004D930
468 * Grafic controller - Do not map below 2 GB in address space, because this
469 * area is used for SDRAM autosizing.
471 #define SM501_FB_BASE 0xE0000000
472 #define CFG_CS1_START (SM501_FB_BASE)
473 #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
474 #define CFG_CS1_CFG 0x8F48FF70
475 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
477 #define CFG_CS_BURST 0x00000000
478 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
480 #define CFG_RESET_ADDRESS 0xff000000
482 /*-----------------------------------------------------------------------
484 *-----------------------------------------------------------------------
486 #define CONFIG_USB_CLOCK 0x0001BBBB
487 #define CONFIG_USB_CONFIG 0x00001000
489 /*-----------------------------------------------------------------------
490 * IDE/ATA stuff Supports IDE harddisk
491 *-----------------------------------------------------------------------
494 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
496 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
497 #undef CONFIG_IDE_LED /* LED for ide not supported */
499 #define CONFIG_IDE_RESET /* reset for ide supported */
500 #define CONFIG_IDE_PREINIT
502 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
503 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
505 #define CFG_ATA_IDE0_OFFSET 0x0000
507 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
509 /* Offset for data I/O */
510 #define CFG_ATA_DATA_OFFSET (0x0060)
512 /* Offset for normal register accesses */
513 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
515 /* Offset for alternate registers */
516 #define CFG_ATA_ALT_OFFSET (0x005C)
518 /* Interval between registers */
519 #define CFG_ATA_STRIDE 4
521 #endif /* __CONFIG_H */