1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
15 #define CONFIG_MPC83xx 1 /* MPC83xx family */
16 #define CONFIG_MPC830x 1 /* MPC830x family */
17 #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
18 #define CONFIG_STRIDER 1 /* STRIDER board specific */
20 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
25 #define CONFIG_83XX_CLKIN 33333333 /* in Hz */
26 #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
29 * Hardware Reset Configuration Word
30 * if CLKIN is 66.66MHz, then
31 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
32 * We choose the A type silicon as default, so the core is 400Mhz.
34 #define CONFIG_SYS_HRCW_LOW (\
35 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
36 HRCWL_DDR_TO_SCB_CLK_2X1 |\
38 HRCWL_CSB_TO_CLKIN_4X1 |\
39 HRCWL_CORE_TO_CSB_3X1)
41 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
42 * in 8308's HRCWH according to the manual, but original Freescale's
43 * code has them and I've expirienced some problems using the board
44 * with BDI3000 attached when I've tried to set these bits to zero
45 * (UART doesn't work after the 'reset run' command).
47 #define CONFIG_SYS_HRCW_HIGH (\
49 HRCWH_PCI1_ARBITER_ENABLE |\
51 HRCWH_FROM_0XFFF00100 |\
52 HRCWH_BOOTSEQ_DISABLE |\
53 HRCWH_SW_WATCHDOG_DISABLE |\
54 HRCWH_ROM_LOC_LOCAL_16BIT |\
55 HRCWH_RL_EXT_LEGACY |\
56 HRCWH_TSEC1M_IN_MII |\
57 HRCWH_TSEC2M_IN_RGMII |\
63 #define CONFIG_SYS_SICRH (\
69 SICRH_IEEE1588_A_GPIO |\
72 SICRH_IEEE1588_B_GPIO |\
77 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
78 #define CONFIG_SYS_SICRL (\
83 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
88 #define CONFIG_SYS_IMMR 0xE0000000
93 #define CONFIG_FSL_SERDES
94 #define CONFIG_FSL_SERDES1 0xe3000
99 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
100 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
101 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
107 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
108 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
109 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
110 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
117 * Manually set up DDR parameters
118 * consist of one chip NT5TU64M16HG from NANYA
121 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
123 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
124 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
125 | CSCONFIG_ODT_RD_NEVER \
126 | CSCONFIG_ODT_WR_ONLY_CURRENT \
127 | CSCONFIG_BANK_BIT_3 \
128 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
130 #define CONFIG_SYS_DDR_TIMING_3 0
131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
132 | (0 << TIMING_CFG0_WRT_SHIFT) \
133 | (0 << TIMING_CFG0_RRT_SHIFT) \
134 | (0 << TIMING_CFG0_WWT_SHIFT) \
135 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
136 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
137 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
138 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
140 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
141 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
142 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
143 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
144 | (9 << TIMING_CFG1_REFREC_SHIFT) \
145 | (2 << TIMING_CFG1_WRREC_SHIFT) \
146 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
147 | (2 << TIMING_CFG1_WRTORD_SHIFT))
149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
150 | (4 << TIMING_CFG2_CPO_SHIFT) \
151 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
152 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
153 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
154 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
155 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
157 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
158 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
160 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
161 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
165 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
166 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
167 | (0x0242 << SDRAM_MODE_SD_SHIFT))
168 /* ODT 150ohm CL=4, AL=0 on SDRAM */
169 #define CONFIG_SYS_DDR_MODE2 0x00000000
174 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
175 #define CONFIG_SYS_MEMTEST_END 0x07f00000
178 * The reserved memory
180 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
182 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
183 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
186 * Initial RAM Base Address Setup
188 #define CONFIG_SYS_INIT_RAM_LOCK 1
189 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
190 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
191 #define CONFIG_SYS_GBL_DATA_OFFSET \
192 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
195 * Local Bus Configuration & Clock Setup
197 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
198 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
199 #define CONFIG_SYS_LBC_LBCR 0x00040000
202 * FLASH on the Local Bus
204 #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
205 #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
206 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
207 #define CONFIG_FLASH_CFI_LEGACY
208 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
210 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
211 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
212 #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
214 /* Window base at flash base */
215 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
216 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
218 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
219 | BR_PS_16 /* 16 bit port */ \
220 | BR_MS_GPCM /* MSEL = GPCM */ \
222 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
231 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
232 #define CONFIG_SYS_MAX_FLASH_SECT 135
234 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
235 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
240 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
241 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
243 /* Window base at FPGA base */
244 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
245 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
247 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
248 | BR_PS_16 /* 16 bit port */ \
249 | BR_MS_GPCM /* MSEL = GPCM */ \
252 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
256 | OR_GPCM_TRLX_CLEAR \
257 | OR_GPCM_EHTR_CLEAR)
259 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
260 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
262 #define CONFIG_SYS_FPGA_COUNT 1
264 #define CONFIG_SYS_MCLINK_MAX 3
266 #define CONFIG_SYS_FPGA_PTR \
267 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
269 #define CONFIG_SYS_FPGA_NO_RFL_HI
274 #define CONFIG_SYS_NS16550_SERIAL
275 #define CONFIG_SYS_NS16550_REG_SIZE 1
276 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
278 #define CONFIG_SYS_BAUDRATE_TABLE \
279 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
281 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
282 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
284 /* Pass open firmware flat tree */
287 #define CONFIG_SYS_I2C
288 #define CONFIG_SYS_I2C_FSL
289 #define CONFIG_SYS_FSL_I2C_SPEED 400000
290 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
291 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
293 #define CONFIG_PCA953X /* NXP PCA9554 */
294 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
295 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
297 #define CONFIG_PCA9698 /* NXP PCA9698 */
299 #define CONFIG_SYS_I2C_IHS
300 #define CONFIG_SYS_I2C_IHS_CH0
301 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
302 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
303 #define CONFIG_SYS_I2C_IHS_CH1
304 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
305 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
306 #define CONFIG_SYS_I2C_IHS_CH2
307 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
308 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
309 #define CONFIG_SYS_I2C_IHS_CH3
310 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
311 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
313 #ifdef CONFIG_STRIDER_CON_DP
314 #define CONFIG_SYS_I2C_IHS_DUAL
315 #define CONFIG_SYS_I2C_IHS_CH0_1
316 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
317 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
318 #define CONFIG_SYS_I2C_IHS_CH1_1
319 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
320 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
321 #define CONFIG_SYS_I2C_IHS_CH2_1
322 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
323 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
324 #define CONFIG_SYS_I2C_IHS_CH3_1
325 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
326 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
330 * Software (bit-bang) I2C driver configuration
332 #define CONFIG_SYS_I2C_SOFT
333 #define CONFIG_SOFT_I2C_READ_REPEATED_START
334 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
335 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
336 #define I2C_SOFT_DECLARATIONS2
337 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
338 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
339 #define I2C_SOFT_DECLARATIONS3
340 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
341 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
342 #define I2C_SOFT_DECLARATIONS4
343 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
344 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
345 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
346 #define I2C_SOFT_DECLARATIONS5
347 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
348 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
349 #define I2C_SOFT_DECLARATIONS6
350 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
351 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
352 #define I2C_SOFT_DECLARATIONS7
353 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
354 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
355 #define I2C_SOFT_DECLARATIONS8
356 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
357 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
359 #ifdef CONFIG_STRIDER_CON_DP
360 #define I2C_SOFT_DECLARATIONS9
361 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
362 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
363 #define I2C_SOFT_DECLARATIONS10
364 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
365 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
366 #define I2C_SOFT_DECLARATIONS11
367 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
368 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
369 #define I2C_SOFT_DECLARATIONS12
370 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
371 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
374 #ifdef CONFIG_STRIDER_CON
375 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
376 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
377 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
378 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
379 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
381 #elif defined(CONFIG_STRIDER_CON_DP)
382 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
383 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
384 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
385 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
386 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
388 #elif defined(CONFIG_STRIDER_CPU_DP)
389 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
390 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
391 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
392 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
395 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
396 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
397 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
398 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
403 void fpga_gpio_set(unsigned int bus, int pin);
404 void fpga_gpio_clear(unsigned int bus, int pin);
405 int fpga_gpio_get(unsigned int bus, int pin);
406 void fpga_control_set(unsigned int bus, int pin);
407 void fpga_control_clear(unsigned int bus, int pin);
410 #ifdef CONFIG_STRIDER_CON
411 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
412 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
413 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
414 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
415 #elif defined(CONFIG_STRIDER_CON_DP)
416 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
417 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
418 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
420 #define I2C_SDA_GPIO 0x0040
421 #define I2C_SCL_GPIO 0x0020
422 #define I2C_FPGA_IDX I2C_ADAP_HWNR
425 #ifdef CONFIG_STRIDER_CON_DP
428 if (I2C_ADAP_HWNR > 7) \
429 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
431 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
434 #define I2C_ACTIVE { }
437 #define I2C_TRISTATE { }
439 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
440 #define I2C_SDA(bit) \
443 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
445 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
447 #define I2C_SCL(bit) \
450 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
452 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
454 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
457 * Software (bit-bang) MII driver configuration
459 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
460 #define CONFIG_BITBANGMII_MULTI
465 #define CONFIG_SYS_OSD_SCREENS 1
466 #define CONFIG_SYS_DP501_DIFFERENTIAL
467 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
469 #ifdef CONFIG_STRIDER_CON_DP
470 #define CONFIG_SYS_OSD_DH
475 * Addresses are mapped 1-1.
477 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
478 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
479 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
480 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
481 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
482 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
483 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
484 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
485 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
487 /* enable PCIE clock */
488 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
490 #define CONFIG_PCI_INDIRECT_BRIDGE
493 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
494 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
499 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
500 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
503 * TSEC ethernet configuration
505 #define CONFIG_MII 1 /* MII PHY management */
507 #define CONFIG_TSEC1_NAME "eTSEC0"
508 #define TSEC1_PHY_ADDR 1
509 #define TSEC1_PHYIDX 0
510 #define TSEC1_FLAGS 0
512 /* Options are: eTSEC[0-1] */
513 #define CONFIG_ETHPRIME "eTSEC0"
519 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
520 CONFIG_SYS_MONITOR_LEN)
521 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
522 #define CONFIG_ENV_SIZE 0x2000
523 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
524 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
526 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
529 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
530 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
533 * Command line configuration.
537 * Miscellaneous configurable options
539 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
540 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
542 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
544 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
547 * For booting Linux, the board info and command line data
548 * have to be in the first 256 MB of memory, since this is
549 * the maximum mapped by the Linux kernel during initialization.
551 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
556 #define CONFIG_SYS_HID0_INIT 0x000000000
557 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
558 HID0_ENABLE_INSTRUCTION_CACHE | \
559 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
560 #define CONFIG_SYS_HID2 HID2_HBE
566 /* DDR: cache cacheable */
567 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
569 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
571 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
572 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
574 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
575 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
576 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
577 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
579 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
580 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
582 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
583 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
585 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
587 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
588 BATL_CACHEINHIBIT | \
590 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
592 /* Stack in dcache: cacheable, no memory coherence */
593 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
594 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
596 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
597 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
600 * Environment Configuration
603 #define CONFIG_ENV_OVERWRITE
605 #if defined(CONFIG_TSEC_ENET)
606 #define CONFIG_HAS_ETH0
609 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
612 #define CONFIG_HOSTNAME "hrcon"
613 #define CONFIG_ROOTPATH "/opt/nfsroot"
614 #define CONFIG_BOOTFILE "uImage"
616 #define CONFIG_PREBOOT /* enable preboot variable */
618 #define CONFIG_EXTRA_ENV_SETTINGS \
620 "consoledev=ttyS1\0" \
621 "u-boot=u-boot.bin\0" \
622 "kernel_addr=1000000\0" \
623 "fdt_addr=C00000\0" \
624 "fdtfile=hrcon.dtb\0" \
625 "load=tftp ${loadaddr} ${u-boot}\0" \
626 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
627 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
628 " +${filesize};cp.b ${fileaddr} " \
629 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
630 "upd=run load update\0" \
632 #define CONFIG_NFSBOOTCOMMAND \
633 "setenv bootargs root=/dev/nfs rw " \
634 "nfsroot=$serverip:$rootpath " \
635 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
636 "console=$consoledev,$baudrate $othbootargs;" \
637 "tftp ${kernel_addr} $bootfile;" \
638 "tftp ${fdt_addr} $fdtfile;" \
639 "bootm ${kernel_addr} - ${fdt_addr}"
641 #define CONFIG_MMCBOOTCOMMAND \
642 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
643 "console=$consoledev,$baudrate $othbootargs;" \
644 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
645 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
646 "bootm ${kernel_addr} - ${fdt_addr}"
648 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
650 #endif /* __CONFIG_H */