2 * (C) Copyright 2005 Embedded Alley Solutions, Inc.
3 * Dan Malek <dan@embeddedalley.com>
5 * Updates for Silicon Tx GP3 SSA board.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 /* mpc8560ads board configuration file */
30 /* please refer to doc/README.mpc85xx for more info */
31 /* make sure you change the MAC address and other network params first,
32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
38 /* High Level Configuration Options */
39 #define CONFIG_BOOKE 1 /* BOOKE */
40 #define CONFIG_E500 1 /* BOOKE e500 family */
41 #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
42 #define CONFIG_CPM2 1 /* has CPM2 */
43 #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
45 #undef CONFIG_PCI /* pci ethernet support */
46 #define CONFIG_TSEC_ENET /* tsec ethernet support*/
47 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
48 #define CONFIG_ENV_OVERWRITE
49 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
50 #undef CONFIG_DDR_ECC /* only for ECC DDR module */
51 #undef CONFIG_DDR_DLL /* possible DLL fix needed */
52 #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
58 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
60 /* Blinkin' LEDs for Robert :-)
62 #define CONFIG_SHOW_ACTIVITY 1
65 * These can be toggled for performance analysis, otherwise use default.
67 #define CONFIG_L2_CACHE /* toggle L2 cache */
68 #define CONFIG_BTB /* toggle branch predition */
69 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */
71 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
73 #undef CFG_DRAM_TEST /* memory test, takes time */
74 #define CFG_MEMTEST_START 0x00200000 /* memtest region */
75 #define CFG_MEMTEST_END 0x00400000
78 /* Localbus connector. There are many options that can be
79 * connected here, including sdram or lots of flash.
80 * This address, however, is used to configure a 256M local bus
81 * window that includes the Config latch below.
83 #define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */
84 #define CFG_LBC_OPTION_SIZE 256 /* 256MB */
86 /* There are various flash options used, we configure for the largest,
87 * which is 64Mbytes. The CFI works fine and will discover the proper
90 #define CFG_FLASH_BASE 0xFC000000 /* start of FLASH 64M */
91 #define CFG_BR0_PRELIM 0xFC001801 /* port size 32bit */
92 #define CFG_OR0_PRELIM 0xFC000FF7 /* 64 MB Flash */
94 #define CFG_FLASH_CFI 1
95 #define CFG_FLASH_CFI_DRIVER 1
96 #undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
97 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
98 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
100 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
102 #define CFG_FLASH_PROTECTION
104 /* The configuration latch is Chip Select 1.
105 * It's an 8-bit latch in the lower 8 bits of the word.
107 #define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */
108 #define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */
109 #define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
111 #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
113 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
120 #define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
122 #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
124 #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
125 #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
133 * Base addresses -- Note these are effective addresses where the
134 * actual resources get mapped (not physical addresses)
136 #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
137 #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
139 #define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
141 #undef CONFIG_CLOCKS_IN_MHZ
143 /* local bus definitions */
144 #define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
145 #define CFG_OR2_PRELIM 0xfc006901
146 #define CFG_LBC_LCRR 0x00030004 /* local bus freq */
147 #define CFG_LBC_LBCR 0x00000000
148 #define CFG_LBC_LSRT 0x20000000
149 #define CFG_LBC_MRTPR 0x20000000
150 #define CFG_LBC_LSDMR_1 0x2861b723
151 #define CFG_LBC_LSDMR_2 0x0861b723
152 #define CFG_LBC_LSDMR_3 0x0861b723
153 #define CFG_LBC_LSDMR_4 0x1861b723
154 #define CFG_LBC_LSDMR_5 0x4061b723
156 #define CONFIG_L1_INIT_RAM
157 #define CFG_INIT_RAM_LOCK 1
158 #define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
159 #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
161 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
162 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
163 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
165 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
166 #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
169 #define CONFIG_CONS_INDEX 2
170 #undef CONFIG_SERIAL_SOFTWARE_FIFO
172 #define CFG_NS16550_SERIAL
173 #define CFG_NS16550_REG_SIZE 1
174 #define CFG_NS16550_CLK get_bus_freq(0)
176 #define CFG_BAUDRATE_TABLE \
177 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
179 #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
180 #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
182 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
183 #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
184 #ifdef CFG_HUSH_PARSER
185 #define CFG_PROMPT_HUSH_PS2 "> "
189 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
190 #define CONFIG_HARD_I2C /* I2C with hardware support*/
191 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
192 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
193 #define CFG_I2C_SLAVE 0x7F
195 #define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
197 /* I did the 'if 0' so we could keep the syntax above if ever needed. */
198 #undef CFG_I2C_NOPROBES
200 #define CFG_I2C_OFFSET 0x3000
202 /* I2C EEPROM. AT24C32, we keep our environment in here.
204 #define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
205 #define CFG_I2C_EEPROM_ADDR_LEN 2
206 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
207 #define CFG_EEPROM_PAGE_WRITE_ENABLE
208 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
211 * Standard 8555 PCI mapping.
212 * Addresses are mapped 1-1.
214 #define CFG_PCI1_MEM_BASE 0x80000000
215 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
216 #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
217 #define CFG_PCI1_IO_BASE 0x00000000
218 #define CFG_PCI1_IO_PHYS 0xe2000000
219 #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
221 #define CFG_PCI2_MEM_BASE 0xa0000000
222 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
223 #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
224 #define CFG_PCI2_IO_BASE 0x00000000
225 #define CFG_PCI2_IO_PHYS 0xe3000000
226 #define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
228 #if defined(CONFIG_PCI) /* PCI Ethernet card */
230 #define CONFIG_NET_MULTI
231 #define CONFIG_PCI_PNP /* do pci plug-and-play */
233 #undef CONFIG_EEPRO100
236 #if !defined(CONFIG_PCI_PNP)
237 #define PCI_ENET0_IOADDR 0xe0000000
238 #define PCI_ENET0_MEMADDR 0xe0000000
239 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
242 #undef CONFIG_PCI_SCAN_SHOW
243 #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
245 #endif /* CONFIG_PCI */
247 #if defined(CONFIG_TSEC_ENET)
249 #ifndef CONFIG_NET_MULTI
250 #define CONFIG_NET_MULTI 1
253 #define CONFIG_MII 1 /* MII PHY management */
255 #define CONFIG_MPC85XX_TSEC1 1
256 #define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
257 #define CONFIG_MPC85XX_TSEC2 1
258 #define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
259 #undef CONFIG_MPS85XX_FEC
261 #define TSEC1_PHY_ADDR 2
262 #define TSEC2_PHY_ADDR 4
263 #define TSEC1_PHYIDX 0
264 #define TSEC2_PHYIDX 0
265 #define CONFIG_ETHPRIME "TSEC0"
267 #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
269 #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
270 #undef CONFIG_ETHER_NONE /* define if ether on something else */
271 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
273 #if (CONFIG_ETHER_INDEX == 2)
277 * - Select bus for bd/buffers
280 #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
281 #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
282 #define CFG_CPMFCR_RAMTYPE 0
284 #define CFG_FCC_PSMR (FCC_PSMR_FDE)
286 #define CFG_FCC_PSMR 0
288 #define FETH2_RST 0x01
289 #elif (CONFIG_ETHER_INDEX == 3)
290 /* need more definitions here for FE3 */
291 #define FETH3_RST 0x80
292 #endif /* CONFIG_ETHER_INDEX */
294 /* MDIO is done through the TSEC0 control.
296 #define CONFIG_MII /* MII PHY management */
297 #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
301 /* Environment - default config is in flash, see below */
302 #if 0 /* in EEPROM */
303 #define CFG_ENV_IS_IN_EEPROM 1
304 #define CFG_ENV_OFFSET 0
305 #define CFG_ENV_SIZE 2048
307 #define CFG_ENV_IS_IN_FLASH 1
308 #define CFG_ENV_SECT_SIZE 0x40000
310 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
311 #define CFG_ENV_SIZE 0x4000
312 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
313 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
316 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
317 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
319 #define CONFIG_TIMESTAMP /* Print image info with ts */
321 #if defined(CFG_RAMBOOT)
322 #if defined(CONFIG_PCI)
323 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
324 CFG_CMD_PING | CFG_CMD_I2C) & \
327 #elif defined(CONFIG_TSEC_ENET)
328 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
329 CFG_CMD_MII | CFG_CMD_I2C ) & \
331 #elif defined(CONFIG_ETHER_ON_FCC)
332 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
333 CFG_CMD_PING | CFG_CMD_I2C) & \
337 #if defined(CONFIG_PCI)
338 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
339 CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
340 #elif defined(CONFIG_TSEC_ENET)
341 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
342 CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C)
343 #elif defined(CONFIG_ETHER_ON_FCC)
344 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
345 CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C)
348 #include <cmd_confdefs.h>
350 #undef CONFIG_WATCHDOG /* watchdog disabled */
353 * Miscellaneous configurable options
355 #define CFG_LONGHELP /* undef to save memory */
356 #define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */
357 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
358 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
360 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
362 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
363 #define CFG_MAXARGS 16 /* max number of command args */
364 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
365 #define CFG_LOAD_ADDR 0x1000000 /* default load address */
366 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
369 * For booting Linux, the board info and command line data
370 * have to be in the first 8 MB of memory, since this is
371 * the maximum mapped by the Linux kernel during initialization.
373 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
375 /* Cache Configuration */
376 #define CFG_DCACHE_SIZE 32768
377 #define CFG_CACHELINE_SIZE 32
378 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
379 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
383 * Internal Definitions
387 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
388 #define BOOTFLAG_WARM 0x02 /* Software reboot */
390 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
391 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
392 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
395 /*Note: change below for your network setting!!! */
396 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
397 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
398 #define CONFIG_HAS_ETH1
399 #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
400 #define CONFIG_HAS_ETH2
401 #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
405 * Environment in EEPROM is compatible with different flash sector sizes,
406 * but only little space is available, so we use a very simple setup.
407 * With environment in flash, we use a more powerful default configuration.
409 #ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
411 #define CONFIG_BAUDRATE 38400
413 #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
414 #define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
415 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
416 #define CONFIG_SERVERIP 192.168.85.1
417 #define CONFIG_IPADDR 192.168.85.60
418 #define CONFIG_GATEWAYIP 192.168.85.1
419 #define CONFIG_NETMASK 255.255.255.0
420 #define CONFIG_HOSTNAME STX_SSA
421 #define CONFIG_ROOTPATH /gppproot
422 #define CONFIG_BOOTFILE uImage
423 #define CONFIG_LOADADDR 0x1000000
425 #else /* ENV IS IN FLASH -- use a full-blown envionment */
427 #define CONFIG_BAUDRATE 115200
429 #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
431 #define CONFIG_PREBOOT "echo;" \
432 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
435 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
437 #define CONFIG_EXTRA_ENV_SETTINGS \
438 "hostname=gp3ssa\0" \
439 "bootfile=/tftpboot/gp3ssa/uImage\0" \
440 "loadaddr=400000\0" \
443 "nfsargs=setenv bootargs root=/dev/nfs rw " \
444 "nfsroot=$serverip:$rootpath\0" \
445 "ramargs=setenv bootargs root=/dev/ram rw\0" \
446 "addip=setenv bootargs $bootargs " \
447 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
448 ":$hostname:$netdev:off panic=1\0" \
449 "addcons=setenv bootargs $bootargs " \
450 "console=$consdev,$baudrate\0" \
451 "flash_nfs=run nfsargs addip addcons;" \
452 "bootm $kernel_addr\0" \
453 "flash_self=run ramargs addip addcons;" \
454 "bootm $kernel_addr $ramdisk_addr\0" \
455 "net_nfs=tftp $loadaddr $bootfile;" \
456 "run nfsargs addip addcons;bootm\0" \
457 "rootpath=/opt/eldk/ppc_85xx\0" \
458 "kernel_addr=FC000000\0" \
459 "ramdisk_addr=FC200000\0" \
461 #define CONFIG_BOOTCOMMAND "run flash_self"
463 #endif /* CFG_ENV_IS_IN_EEPROM */
465 #endif /* __CONFIG_H */