2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
26 * U-Boot port on STx XTc 8xx board
27 * Mostly copied from Panto's NETTA2 board.
34 * High Level Configuration Options
38 #define CONFIG_MPC875 1 /* This is a MPC875 CPU */
39 #define CONFIG_STXXTC 1 /* ...on a STx XTc board */
41 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42 #undef CONFIG_8xx_CONS_SMC2
43 #undef CONFIG_8xx_CONS_NONE
45 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */
47 #define CONFIG_XIN 10000000 /* 10 MHz input xtal */
49 /* Select one of few clock rates defined later in this file.
51 /* #define MPC8XX_HZ 50000000 */
52 #define MPC8XX_HZ 66666666
54 #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
57 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
59 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
62 #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
64 #undef CONFIG_BOOTARGS
65 #define CONFIG_BOOTCOMMAND \
67 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
68 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
71 #define CONFIG_AUTOSCRIPT
72 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
73 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
75 #undef CONFIG_WATCHDOG /* watchdog disabled */
77 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
78 #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
80 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
82 #undef CONFIG_MAC_PARTITION
83 #undef CONFIG_DOS_PARTITION
85 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
87 #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
88 #define FEC_ENET 1 /* eth.c needs it that way... */
89 #undef CFG_DISCOVER_PHY
93 #define CONFIG_ETHER_ON_FEC1 1
94 #define CONFIG_FEC1_PHY 1 /* phy address of FEC */
95 #undef CONFIG_FEC1_PHY_NORXERR
97 #define CONFIG_ETHER_ON_FEC2 1
98 #define CONFIG_FEC2_PHY 3
99 #undef CONFIG_FEC2_PHY_NORXERR
101 #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
103 #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
110 #define CONFIG_BOARD_EARLY_INIT_F 1
111 #define CONFIG_MISC_INIT_R
113 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
114 #include <cmd_confdefs.h>
117 * Miscellaneous configurable options
119 #define CFG_LONGHELP /* undef to save memory */
120 #define CFG_PROMPT "xtc> " /* Monitor Command Prompt */
122 #define CFG_HUSH_PARSER 1
123 #define CFG_PROMPT_HUSH_PS2 "> "
125 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
126 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
128 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
130 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
131 #define CFG_MAXARGS 16 /* max number of command args */
132 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
134 #define CFG_MEMTEST_START 0x0300000 /* memtest works on */
135 #define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
137 #define CFG_LOAD_ADDR 0x100000 /* default load address */
139 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
141 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
144 * Low Level Configuration Settings
145 * (address mappings, register initial values, etc.)
146 * You should know what you are doing if you make changes here.
148 /*-----------------------------------------------------------------------
149 * Internal Memory Mapped Register
151 #define CFG_IMMR 0xFF000000
153 /*-----------------------------------------------------------------------
154 * Definitions for initial stack pointer and data area (in DPRAM)
156 #define CFG_INIT_RAM_ADDR CFG_IMMR
157 #define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
158 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
159 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
160 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
162 /*-----------------------------------------------------------------------
163 * Start addresses for the final memory configuration
164 * (Set up by the startup code)
165 * Please note that CFG_SDRAM_BASE _must_ start at 0
167 #define CFG_SDRAM_BASE 0x00000000
168 #define CFG_FLASH_BASE 0x40000000
170 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
172 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
175 /* yes this is weird, I know :) */
176 #define CFG_MONITOR_BASE (CFG_FLASH_BASE | 0x00F00000)
177 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
179 #define CFG_RESET_ADDRESS 0x80000000
182 * For booting Linux, the board info and command line data
183 * have to be in the first 8 MB of memory, since this is
184 * the maximum mapped by the Linux kernel during initialization.
186 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
188 /*-----------------------------------------------------------------------
191 #define CFG_ENV_IS_IN_FLASH 1
192 #define CFG_ENV_SECT_SIZE 0x10000
194 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000)
195 #define CFG_ENV_OFFSET 0
196 #define CFG_ENV_SIZE 0x4000
198 #define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000)
199 #define CFG_ENV_OFFSET_REDUND 0
200 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
202 #define CFG_FLASH_CFI 1
203 #define CFG_FLASH_CFI_DRIVER 1
204 #undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
205 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
206 #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
208 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 }
210 #define CFG_FLASH_PROTECTION
212 /*-----------------------------------------------------------------------
213 * Cache Configuration
215 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
216 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
217 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
220 /*-----------------------------------------------------------------------
221 * SYPCR - System Protection Control 11-9
222 * SYPCR can only be written once after reset!
223 *-----------------------------------------------------------------------
224 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
226 #if defined(CONFIG_WATCHDOG)
227 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
228 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
230 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
233 /*-----------------------------------------------------------------------
234 * SIUMCR - SIU Module Configuration 11-6
235 *-----------------------------------------------------------------------
236 * PCMCIA config., multi-function pin tri-state
238 #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
240 /*-----------------------------------------------------------------------
241 * TBSCR - Time Base Status and Control 11-26
242 *-----------------------------------------------------------------------
243 * Clear Reference Interrupt Status, Timebase freezing enabled
245 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
247 /*-----------------------------------------------------------------------
248 * RTCSC - Real-Time Clock Status and Control Register 11-27
249 *-----------------------------------------------------------------------
251 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
253 /*-----------------------------------------------------------------------
254 * PISCR - Periodic Interrupt Status and Control 11-31
255 *-----------------------------------------------------------------------
256 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
258 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
260 /*-----------------------------------------------------------------------
261 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
262 *-----------------------------------------------------------------------
263 * Reset PLL lock status sticky bit, timer expired status bit and timer
264 * interrupt status bit
268 #if CONFIG_XIN == 10000000
270 #if MPC8XX_HZ == 50000000
271 #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
272 (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
274 #elif MPC8XX_HZ == 66666666
275 #define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
276 (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
279 #error unsupported CPU freq for XIN = 10MHz
282 #error unsupported freq for XIN (must be 10MHz)
287 *-----------------------------------------------------------------------
288 * SCCR - System Clock and reset Control Register 15-27
289 *-----------------------------------------------------------------------
290 * Set clock output, timebase and RTC source and divider,
291 * power management and some other internal clocks
293 * Note: When TBS == 0 the timebase is independent of current cpu clock.
296 #define SCCR_MASK SCCR_EBDF11
297 #if MPC8XX_HZ > 66666666
298 #define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
299 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
300 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
301 SCCR_DFALCD00 | SCCR_EBDF01)
303 #define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
304 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
305 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
309 /*-----------------------------------------------------------------------
311 *-----------------------------------------------------------------------
314 /*#define CFG_DER 0x2002000F*/
318 * Init Memory Controller:
320 * BR0/1 and OR0/1 (FLASH)
323 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
324 #define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
326 /* used to re-map FLASH both when starting from SRAM or FLASH:
327 * restrict access enough to keep SRAM working (if any)
328 * but not too much to meddle with FLASH accesses
331 #define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
333 #define CFG_REMAP_OR_AM 0x80000000
334 #define CFG_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
336 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
337 #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
339 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
340 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
341 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
343 #define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH)
344 #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
347 * BR4 and OR4 (SDRAM)
350 #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
351 #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
353 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
354 #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
356 #define CFG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
357 #define CFG_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
360 * Memory Periodic Timer Prescaler
364 * Memory Periodic Timer Prescaler
366 * The Divider for PTA (refresh timer) configuration is based on an
367 * example SDRAM configuration (64 MBit, one bank). The adjustment to
368 * the number of chip selects (NCS) and the actually needed refresh
369 * rate is done by setting MPTPR.
371 * PTA is calculated from
372 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
374 * gclk CPU clock (not bus clock!)
375 * Trefresh Refresh cycle * 4 (four word bursts used)
377 * 4096 Rows from SDRAM example configuration
378 * 1000 factor s -> ms
379 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
380 * 4 Number of refresh cycles per period
381 * 64 Refresh cycle in ms per number of rows
382 * --------------------------------------------
383 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
385 * 50 MHz => 50.000.000 / Divider = 98
386 * 66 Mhz => 66.000.000 / Divider = 129
387 * 80 Mhz => 80.000.000 / Divider = 156
390 #define CFG_MAMR_PTA 234
393 * For 16 MBit, refresh rates could be 31.3 us
394 * (= 64 ms / 2K = 125 / quad bursts).
395 * For a simpler initialization, 15.6 us is used instead.
397 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
398 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
400 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
401 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
403 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
404 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
405 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
408 * MAMR settings for SDRAM
412 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
413 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
414 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
417 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
418 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
419 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
422 * Internal Definitions
426 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
427 #define BOOTFLAG_WARM 0x02 /* Software reboot */
429 #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
431 /****************************************************************/
433 #define NAND_SIZE 0x00010000 /* 64K */
434 #define NAND_BASE 0xF1000000
436 /****************************************************************/
439 #define CFG_NAND_BASE NAND_BASE
440 #define CONFIG_MTD_NAND_ECC_JFFS2
441 #define CONFIG_MTD_NAND_VERIFY_WRITE
442 #define CONFIG_MTD_NAND_UNSAFE
444 #define CFG_MAX_NAND_DEVICE 1
447 #define SECTORSIZE 512
448 #define ADDR_COLUMN 1
450 #define ADDR_COLUMN_PAGE 3
451 #define NAND_ChipID_UNKNOWN 0x00
452 #define NAND_MAX_FLOORS 1
453 #define NAND_MAX_CHIPS 1
455 /* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */
456 #define NAND_DISABLE_CE(nand) \
458 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \
461 #define NAND_ENABLE_CE(nand) \
463 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \
466 #define NAND_CTL_CLRALE(nandptr) \
468 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \
471 #define NAND_CTL_SETALE(nandptr) \
473 (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \
476 #define NAND_CTL_CLRCLE(nandptr) \
478 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \
481 #define NAND_CTL_SETCLE(nandptr) \
483 (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \
487 #define NAND_WAIT_READY(nand) \
490 while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \
491 if (++_tries > 100000) \
495 #define NAND_WAIT_READY(nand) udelay(12)
498 #define WRITE_NAND_COMMAND(d, adr) \
500 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
503 #define WRITE_NAND_ADDRESS(d, adr) \
505 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
508 #define WRITE_NAND(d, adr) \
510 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
513 #define READ_NAND(adr) \
514 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
516 /*****************************************************************************/
518 #define CFG_DIRECT_FLASH_TFTP
519 #define CFG_DIRECT_NAND_TFTP
521 /*****************************************************************************/
523 /* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
524 * CxOE and CxRESET. We use the CxOE.
526 #define STATUS_LED_BIT 0x00000080 /* bit 24 */
528 #define STATUS_LED_PERIOD (CFG_HZ / 2)
529 #define STATUS_LED_STATE STATUS_LED_BLINKING
531 #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
532 #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
538 /* led_id_t is unsigned int mask */
539 typedef unsigned int led_id_t;
541 #define __led_toggle(_msk) \
543 ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
546 #define __led_set(_msk, _st) \
549 ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
551 ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
554 #define __led_init(msk, st) __led_set(msk, st)
558 /******************************************************************************/
560 #define CFG_CONSOLE_IS_IN_ENV 1
561 #define CFG_CONSOLE_OVERWRITE_ROUTINE 1
562 #define CFG_CONSOLE_ENV_OVERWRITE 1
564 /******************************************************************************/
566 /* use board specific hardware */
567 #undef CONFIG_WATCHDOG /* watchdog disabled */
568 #define CONFIG_HW_WATCHDOG
569 #define CONFIG_SHOW_ACTIVITY
571 /*****************************************************************************/
573 #define CONFIG_AUTO_COMPLETE 1
574 #define CONFIG_CRC32_VERIFY 1
575 #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
577 /* Note: change below for your network setting!!!
578 * This was done just to facilitate manufacturing test and configuration.
580 #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
582 #define CONFIG_SERVERIP 192.168.08.1
583 #define CONFIG_IPADDR 192.168.08.85
584 #define CONFIG_GATEWAYIP 192.168.08.1
585 #define CONFIG_NETMASK 255.255.255.0
586 #define CONFIG_HOSTNAME stx_xtc
587 #define CONFIG_ROOTPATH /xtcroot
588 #define CONFIG_BOOTFILE uImage
589 #define CONFIG_LOADADDR 0x1000000
592 #endif /* __CONFIG_H */