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1 /*
2  * Configuration settings for the TechNexion TAO-3530 SOM
3  * equipped on Thunder baseboard.
4  *
5  * Edward Lin <linuxfae@technexion.com>
6  * Tapani Utriainen <linuxfae@technexion.com>
7  *
8  * Copyright (C) 2013 Stefan Roese <sr@denx.de>
9  *
10  * SPDX-License-Identifier:     GPL-2.0+
11  */
12
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15
16 /*
17  * High Level Configuration Options
18  */
19 #define CONFIG_OMAP                     /* in a TI OMAP core */
20
21 #define CONFIG_OMAP_GPIO
22 #define CONFIG_OMAP_COMMON
23 /* Common ARM Erratas */
24 #define CONFIG_ARM_ERRATA_454179
25 #define CONFIG_ARM_ERRATA_430973
26 #define CONFIG_ARM_ERRATA_621766
27
28 #define MACH_TYPE_OMAP3_TAO3530         2836
29
30 #define CONFIG_SDRC                     /* Has an SDRC controller */
31
32 #include <asm/arch/cpu.h>               /* get chip and board defs */
33 #include <asm/arch/omap.h>
34
35 /*
36  * Display CPU and Board information
37  */
38 #define CONFIG_DISPLAY_CPUINFO
39 #define CONFIG_DISPLAY_BOARDINFO
40
41 /* Clock Defines */
42 #define V_OSCK                  26000000        /* Clock output from T2 */
43 #define V_SCLK                  (V_OSCK >> 1)
44
45 #define CONFIG_MISC_INIT_R
46
47 #define CONFIG_OF_LIBFDT
48
49 #define CONFIG_CMDLINE_TAG
50 #define CONFIG_SETUP_MEMORY_TAGS
51 #define CONFIG_INITRD_TAG
52 #define CONFIG_REVISION_TAG
53
54 /*
55  * Size of malloc() pool
56  */
57 #define CONFIG_SYS_MALLOC_LEN           (4 << 20)
58 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB sector */
59
60 /*
61  * Hardware drivers
62  */
63
64 /*
65  * NS16550 Configuration
66  */
67 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
68
69 #define CONFIG_SYS_NS16550
70 #define CONFIG_SYS_NS16550_SERIAL
71 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
72 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
73
74 /*
75  * select serial console configuration
76  */
77 #define CONFIG_CONS_INDEX               3
78 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
79
80 /* allow to overwrite serial and ethaddr */
81 #define CONFIG_ENV_OVERWRITE
82 #define CONFIG_BAUDRATE                 115200
83 #define CONFIG_GENERIC_MMC
84 #define CONFIG_MMC
85 #define CONFIG_OMAP_HSMMC
86 #define CONFIG_DOS_PARTITION
87
88 /* GPIO banks */
89 #define CONFIG_OMAP3_GPIO_2             /* GPIO32 ..63  is in GPIO bank 2 */
90 #define CONFIG_OMAP3_GPIO_3             /* GPIO64 ..95  is in GPIO bank 3 */
91 #define CONFIG_OMAP3_GPIO_4             /* GPIO96 ..127 is in GPIO bank 4 */
92 #define CONFIG_OMAP3_GPIO_5             /* GPIO128..159 is in GPIO bank 5 */
93 #define CONFIG_OMAP3_GPIO_6             /* GPIO160..191 is in GPIO bank 6 */
94
95 /* commands to include */
96 #define CONFIG_CMD_CACHE
97 #define CONFIG_CMD_EXT2         /* EXT2 Support                 */
98 #define CONFIG_CMD_FAT          /* FAT support                  */
99 #define CONFIG_CMD_MTDPARTS     /* Enable MTD parts commands */
100 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
101 #define MTDIDS_DEFAULT                  "nand0=nand"
102 #define MTDPARTS_DEFAULT                "mtdparts=nand:512k(x-loader),"\
103                                         "1920k(u-boot),128k(u-boot-env),"\
104                                         "4m(kernel),-(fs)"
105
106 #define CONFIG_CMD_I2C          /* I2C serial bus support       */
107 #define CONFIG_CMD_MMC          /* MMC support                  */
108 #define CONFIG_CMD_NAND         /* NAND support                 */
109 #define CONFIG_CMD_DHCP
110 #define CONFIG_CMD_PING
111
112 #define CONFIG_SYS_NO_FLASH
113 #define CONFIG_SYS_I2C
114 #define CONFIG_SYS_I2C_OMAP34XX
115 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
116 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
117 #define CONFIG_I2C_MULTI_BUS
118
119 /*
120  * TWL4030
121  */
122 #define CONFIG_TWL4030_POWER
123 #define CONFIG_TWL4030_LED
124
125 /*
126  * Board NAND Info.
127  */
128 #define CONFIG_NAND_OMAP_GPMC
129 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
130                                                         /* to access nand */
131 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
132                                                         /* to access nand at */
133                                                         /* CS0 */
134
135 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
136                                                         /* devices */
137 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
138 /* Environment information */
139 #define CONFIG_BOOTDELAY                3
140
141 #define CONFIG_EXTRA_ENV_SETTINGS \
142         "loadaddr=0x82000000\0" \
143         "console=ttyO2,115200n8\0" \
144         "mpurate=600\0" \
145         "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
146         "tv_mode=omapfb.mode=tv:ntsc\0" \
147         "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
148         "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
149         "extra_options= \0" \
150         "mmcdev=0\0" \
151         "mmcroot=/dev/mmcblk0p2 rw\0" \
152         "mmcrootfstype=ext3 rootwait\0" \
153         "nandroot=ubi0:rootfs ubi.mtd=4\0" \
154         "nandrootfstype=ubifs\0" \
155         "mmcargs=setenv bootargs console=${console} " \
156                 "mpurate=${mpurate} " \
157                 "${video_mode} " \
158                 "root=${mmcroot} " \
159                 "rootfstype=${mmcrootfstype} " \
160                 "${extra_options}\0" \
161         "nandargs=setenv bootargs console=${console} " \
162                 "mpurate=${mpurate} " \
163                 "${video_mode} " \
164                 "${network_setting} " \
165                 "root=${nandroot} " \
166                 "rootfstype=${nandrootfstype} "\
167                 "${extra_options}\0" \
168         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
169         "bootscript=echo Running bootscript from mmc ...; " \
170                 "source ${loadaddr}\0" \
171         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
172         "mmcboot=echo Booting from mmc ...; " \
173                 "run mmcargs; " \
174                 "bootm ${loadaddr}\0" \
175         "nandboot=echo Booting from nand ...; " \
176                 "run nandargs; " \
177                 "nand read ${loadaddr} 280000 400000; " \
178                 "bootm ${loadaddr}\0" \
179
180 #define CONFIG_BOOTCOMMAND \
181         "if mmc rescan ${mmcdev}; then " \
182                 "if run loadbootscript; then " \
183                         "run bootscript; " \
184                 "else " \
185                         "if run loaduimage; then " \
186                                 "run mmcboot; " \
187                         "else run nandboot; " \
188                         "fi; " \
189                 "fi; " \
190         "else run nandboot; fi"
191
192 /*
193  * Miscellaneous configurable options
194  */
195 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
196 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
197 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
198
199 /* turn on command-line edit/hist/auto */
200 #define CONFIG_CMDLINE_EDITING
201 #define CONFIG_COMMAND_HISTORY
202 #define CONFIG_AUTO_COMPLETE
203
204 /* Print Buffer Size */
205 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
206                                         sizeof(CONFIG_SYS_PROMPT) + 16)
207 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
208 /* Boot Argument Buffer Size */
209 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
210
211 #define CONFIG_SYS_ALT_MEMTEST          1
212 #define CONFIG_SYS_MEMTEST_START        (0x82000000)            /* memtest */
213                                                                 /* defaults */
214 #define CONFIG_SYS_MEMTEST_END          (0x83FFFFFF)            /* 64MB */
215 #define CONFIG_SYS_MEMTEST_SCRATCH      (0x81000000)    /* dummy address */
216
217 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
218                                                         /* load address */
219 #define CONFIG_SYS_TEXT_BASE            0x80008000
220
221 /*
222  * OMAP3 has 12 GP timers, they can be driven by the system clock
223  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
224  * This rate is divided by a local divisor.
225  */
226 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
227 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
228
229 /*
230  * Stack sizes
231  *
232  * The stack sizes are set up in start.S using the settings below
233  */
234 #define CONFIG_STACKSIZE        (128 << 10)     /* regular stack 128 KiB */
235
236 /*
237  * Physical Memory Map
238  */
239 #define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
240 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
241 #define PHYS_SDRAM_1_SIZE       (32 << 20)      /* at least 32 MiB */
242 #define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
243
244 /*
245  * FLASH and environment organization
246  */
247
248 /* **** PISMO SUPPORT *** */
249 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
250 #define CONFIG_SYS_FLASH_BASE           NAND_BASE
251
252 /* Monitor at start of flash */
253 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
254 #define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
255
256 #define CONFIG_ENV_IS_IN_NAND           1
257 #define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
258 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
259
260 #define CONFIG_SYS_ENV_SECT_SIZE        (128 << 10)
261 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
262 #define CONFIG_ENV_ADDR                 CONFIG_ENV_OFFSET
263
264 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
265 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
266 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
267 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
268                                          CONFIG_SYS_INIT_RAM_SIZE - \
269                                          GENERATED_GBL_DATA_SIZE)
270
271 #define CONFIG_OMAP3_SPI
272
273 /*
274  * USB
275  *
276  * Currently only EHCI is enabled, the MUSB OTG controller
277  * is not enabled.
278  */
279
280 /* USB EHCI */
281 #define CONFIG_CMD_USB
282 #define CONFIG_USB_EHCI
283 #define CONFIG_USB_EHCI_OMAP
284 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO        162
285
286 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
287 #define CONFIG_USB_HOST_ETHER
288 #define CONFIG_USB_ETHER_SMSC95XX
289
290 #define CONFIG_USB_ETHER
291 #define CONFIG_USB_ETHER_RNDIS
292 #define CONFIG_USB_STORAGE
293 #define CONGIG_CMD_STORAGE
294
295 /* Defines for SPL */
296 #define CONFIG_SPL_FRAMEWORK
297 #define CONFIG_SPL_NAND_SIMPLE
298
299 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
300 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
301 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
302 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
303
304 #define CONFIG_SPL_BOARD_INIT
305 #define CONFIG_SPL_LIBCOMMON_SUPPORT
306 #define CONFIG_SPL_LIBDISK_SUPPORT
307 #define CONFIG_SPL_I2C_SUPPORT
308 #define CONFIG_SPL_LIBGENERIC_SUPPORT
309 #define CONFIG_SPL_MMC_SUPPORT
310 #define CONFIG_SPL_FAT_SUPPORT
311 #define CONFIG_SPL_SERIAL_SUPPORT
312 #define CONFIG_SPL_NAND_SUPPORT
313 #define CONFIG_SPL_NAND_BASE
314 #define CONFIG_SPL_NAND_DRIVERS
315 #define CONFIG_SPL_NAND_ECC
316 #define CONFIG_SPL_GPIO_SUPPORT
317 #define CONFIG_SPL_POWER_SUPPORT
318 #define CONFIG_SPL_OMAP3_ID_NAND
319 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
320
321 /* NAND boot config */
322 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
323 #define CONFIG_SYS_NAND_PAGE_COUNT      64
324 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
325 #define CONFIG_SYS_NAND_OOBSIZE         64
326 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
327 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
328 /*
329  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
330  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
331  */
332 #define CONFIG_SYS_NAND_ECCPOS          { 2, 3, 4, 5, 6, 7, 8, 9, \
333                                          10, 11, 12, 13 }
334 #define CONFIG_SYS_NAND_ECCSIZE         512
335 #define CONFIG_SYS_NAND_ECCBYTES        3
336 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
337
338 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
339 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
340
341 #define CONFIG_SPL_TEXT_BASE            0x40200800
342 #define CONFIG_SPL_MAX_SIZE             (54 * 1024)     /* 8 KB for stack */
343
344 /*
345  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
346  * older x-loader implementations. And move the BSS area so that it
347  * doesn't overlap with TEXT_BASE.
348  */
349 #define CONFIG_SYS_TEXT_BASE            0x80008000
350 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
351 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
352
353 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
354 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
355
356 #endif /* __CONFIG_H */