2 * Configuration settings for the TechNexion TAO-3530 SOM
3 * equipped on Thunder baseboard.
5 * Edward Lin <linuxfae@technexion.com>
6 * Tapani Utriainen <linuxfae@technexion.com>
8 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
10 * SPDX-License-Identifier: GPL-2.0+
16 #define CONFIG_SYS_CACHELINE_SIZE 64
19 * High Level Configuration Options
21 #define CONFIG_OMAP /* in a TI OMAP core */
23 #define CONFIG_OMAP_GPIO
24 #define CONFIG_OMAP_COMMON
25 /* Common ARM Erratas */
26 #define CONFIG_ARM_ERRATA_454179
27 #define CONFIG_ARM_ERRATA_430973
28 #define CONFIG_ARM_ERRATA_621766
30 #define MACH_TYPE_OMAP3_TAO3530 2836
32 #define CONFIG_SDRC /* Has an SDRC controller */
34 #include <asm/arch/cpu.h> /* get chip and board defs */
35 #include <asm/arch/omap.h>
38 * Display CPU and Board information
40 #define CONFIG_DISPLAY_CPUINFO
41 #define CONFIG_DISPLAY_BOARDINFO
44 #define V_OSCK 26000000 /* Clock output from T2 */
45 #define V_SCLK (V_OSCK >> 1)
47 #define CONFIG_MISC_INIT_R
49 #define CONFIG_CMDLINE_TAG
50 #define CONFIG_SETUP_MEMORY_TAGS
51 #define CONFIG_INITRD_TAG
52 #define CONFIG_REVISION_TAG
55 * Size of malloc() pool
57 #define CONFIG_SYS_MALLOC_LEN (4 << 20)
58 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
65 * NS16550 Configuration
67 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
69 #define CONFIG_SYS_NS16550_SERIAL
70 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
71 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
74 * select serial console configuration
76 #define CONFIG_CONS_INDEX 3
77 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
79 /* allow to overwrite serial and ethaddr */
80 #define CONFIG_ENV_OVERWRITE
81 #define CONFIG_BAUDRATE 115200
82 #define CONFIG_GENERIC_MMC
84 #define CONFIG_OMAP_HSMMC
85 #define CONFIG_DOS_PARTITION
88 #define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
89 #define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
90 #define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
91 #define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
92 #define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
94 /* commands to include */
95 #define CONFIG_CMD_CACHE
96 #define CONFIG_CMD_EXT2 /* EXT2 Support */
97 #define CONFIG_CMD_FAT /* FAT support */
98 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
99 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
100 #define MTDIDS_DEFAULT "nand0=nand"
101 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
102 "1920k(u-boot),128k(u-boot-env),"\
105 #define CONFIG_CMD_MMC /* MMC support */
106 #define CONFIG_CMD_NAND /* NAND support */
108 #define CONFIG_SYS_NO_FLASH
109 #define CONFIG_SYS_I2C
110 #define CONFIG_SYS_I2C_OMAP34XX
111 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
112 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
113 #define CONFIG_I2C_MULTI_BUS
118 #define CONFIG_TWL4030_POWER
119 #define CONFIG_TWL4030_LED
124 #define CONFIG_NAND_OMAP_GPMC
125 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
127 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
128 /* to access nand at */
131 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
133 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
134 /* Environment information */
135 #define CONFIG_BOOTDELAY 3
137 #define CONFIG_EXTRA_ENV_SETTINGS \
138 "loadaddr=0x82000000\0" \
139 "console=ttyO2,115200n8\0" \
141 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
142 "tv_mode=omapfb.mode=tv:ntsc\0" \
143 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
144 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
145 "extra_options= \0" \
147 "mmcroot=/dev/mmcblk0p2 rw\0" \
148 "mmcrootfstype=ext3 rootwait\0" \
149 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
150 "nandrootfstype=ubifs\0" \
151 "mmcargs=setenv bootargs console=${console} " \
152 "mpurate=${mpurate} " \
155 "rootfstype=${mmcrootfstype} " \
156 "${extra_options}\0" \
157 "nandargs=setenv bootargs console=${console} " \
158 "mpurate=${mpurate} " \
160 "${network_setting} " \
161 "root=${nandroot} " \
162 "rootfstype=${nandrootfstype} "\
163 "${extra_options}\0" \
164 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
165 "bootscript=echo Running bootscript from mmc ...; " \
166 "source ${loadaddr}\0" \
167 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
168 "mmcboot=echo Booting from mmc ...; " \
170 "bootm ${loadaddr}\0" \
171 "nandboot=echo Booting from nand ...; " \
173 "nand read ${loadaddr} 280000 400000; " \
174 "bootm ${loadaddr}\0" \
176 #define CONFIG_BOOTCOMMAND \
177 "if mmc rescan ${mmcdev}; then " \
178 "if run loadbootscript; then " \
181 "if run loaduimage; then " \
183 "else run nandboot; " \
186 "else run nandboot; fi"
189 * Miscellaneous configurable options
191 #define CONFIG_SYS_LONGHELP /* undef to save memory */
192 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
194 /* turn on command-line edit/hist/auto */
195 #define CONFIG_CMDLINE_EDITING
196 #define CONFIG_COMMAND_HISTORY
197 #define CONFIG_AUTO_COMPLETE
199 /* Print Buffer Size */
200 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
201 sizeof(CONFIG_SYS_PROMPT) + 16)
202 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
203 /* Boot Argument Buffer Size */
204 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
206 #define CONFIG_SYS_ALT_MEMTEST 1
207 #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
209 #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
210 #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
212 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
214 #define CONFIG_SYS_TEXT_BASE 0x80008000
217 * OMAP3 has 12 GP timers, they can be driven by the system clock
218 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
219 * This rate is divided by a local divisor.
221 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
222 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
227 * The stack sizes are set up in start.S using the settings below
229 #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
232 * Physical Memory Map
234 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
235 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
236 #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
237 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
240 * FLASH and environment organization
243 /* **** PISMO SUPPORT *** */
244 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
245 #define CONFIG_SYS_FLASH_BASE NAND_BASE
247 /* Monitor at start of flash */
248 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
249 #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
251 #define CONFIG_ENV_IS_IN_NAND 1
252 #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
253 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
255 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
256 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
257 #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
259 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
260 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
261 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
262 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
263 CONFIG_SYS_INIT_RAM_SIZE - \
264 GENERATED_GBL_DATA_SIZE)
266 #define CONFIG_OMAP3_SPI
271 * Currently only EHCI is enabled, the MUSB OTG controller
276 #define CONFIG_USB_EHCI
277 #define CONFIG_USB_EHCI_OMAP
278 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
280 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
281 #define CONFIG_USB_HOST_ETHER
282 #define CONFIG_USB_ETHER_SMSC95XX
284 #define CONFIG_USB_ETHER
285 #define CONFIG_USB_ETHER_RNDIS
286 #define CONFIG_USB_STORAGE
287 #define CONGIG_CMD_STORAGE
289 /* Defines for SPL */
290 #define CONFIG_SPL_FRAMEWORK
291 #define CONFIG_SPL_NAND_SIMPLE
293 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
294 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
295 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
296 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
298 #define CONFIG_SPL_BOARD_INIT
299 #define CONFIG_SPL_LIBCOMMON_SUPPORT
300 #define CONFIG_SPL_LIBDISK_SUPPORT
301 #define CONFIG_SPL_I2C_SUPPORT
302 #define CONFIG_SPL_LIBGENERIC_SUPPORT
303 #define CONFIG_SPL_MMC_SUPPORT
304 #define CONFIG_SPL_FAT_SUPPORT
305 #define CONFIG_SPL_SERIAL_SUPPORT
306 #define CONFIG_SPL_NAND_SUPPORT
307 #define CONFIG_SPL_NAND_BASE
308 #define CONFIG_SPL_NAND_DRIVERS
309 #define CONFIG_SPL_NAND_ECC
310 #define CONFIG_SPL_GPIO_SUPPORT
311 #define CONFIG_SPL_POWER_SUPPORT
312 #define CONFIG_SPL_OMAP3_ID_NAND
313 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
315 /* NAND boot config */
316 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
317 #define CONFIG_SYS_NAND_PAGE_COUNT 64
318 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
319 #define CONFIG_SYS_NAND_OOBSIZE 64
320 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
321 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
323 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
324 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
326 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
328 #define CONFIG_SYS_NAND_ECCSIZE 512
329 #define CONFIG_SYS_NAND_ECCBYTES 3
330 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
332 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
333 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
335 #define CONFIG_SPL_TEXT_BASE 0x40200800
336 #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
339 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
340 * older x-loader implementations. And move the BSS area so that it
341 * doesn't overlap with TEXT_BASE.
343 #define CONFIG_SYS_TEXT_BASE 0x80008000
344 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
345 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
347 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
348 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
350 #endif /* __CONFIG_H */