2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _TEGRA114_COMMON_H_
8 #define _TEGRA114_COMMON_H_
9 #include "tegra-common.h"
11 /* Cortex-A15 uses a cache line size of 64 bytes */
12 #define CONFIG_SYS_CACHELINE_SIZE 64
15 * NS16550 Configuration
17 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
20 * Miscellaneous configurable options
22 #define CONFIG_STACKBASE 0x82800000 /* 40MB */
24 /*-----------------------------------------------------------------------
27 #define CONFIG_SYS_TEXT_BASE 0x80110000
30 * Memory layout for where various images get loaded by boot scripts:
32 * scriptaddr can be pretty much anywhere that doesn't conflict with something
33 * else. Put it above BOOTMAPSZ to eliminate conflicts.
35 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
36 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
38 * kernel_addr_r must be within the first 128M of RAM in order for the
39 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
40 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
41 * should not overlap that area, or the kernel will have to copy itself
42 * somewhere else before decompression. Similarly, the address of any other
43 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
44 * this up to 16M allows for a sizable kernel to be decompressed below the
45 * compressed load address.
47 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
48 * the compressed kernel to be up to 16M too.
50 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
51 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
53 #define CONFIG_LOADADDR 0x81000000
54 #define MEM_LAYOUT_ENV_SETTINGS \
55 "scriptaddr=0x90000000\0" \
56 "pxefile_addr_r=0x90100000\0" \
57 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
58 "fdt_addr_r=0x82000000\0" \
59 "ramdisk_addr_r=0x82100000\0"
62 #define CONFIG_SPL_TEXT_BASE 0x80108000
63 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
64 #define CONFIG_SPL_STACK 0x800ffffc
66 /* For USB EHCI controller */
67 #define CONFIG_EHCI_IS_TDI
68 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
69 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
71 #endif /* _TEGRA114_COMMON_H_ */