2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef _TEGRA20_COMMON_H_
25 #define _TEGRA20_COMMON_H_
26 #include "tegra-common.h"
29 * NS16550 Configuration
31 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
34 * High Level Configuration Options
36 #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
38 /* Environment information, boards can override if required */
39 #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
42 * Miscellaneous configurable options
44 #define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
45 #define CONFIG_STACKBASE 0x02800000 /* 40MB */
47 /*-----------------------------------------------------------------------
50 #define CONFIG_SYS_TEXT_BASE 0x0010E000
53 * Memory layout for where various images get loaded by boot scripts:
55 * scriptaddr can be pretty much anywhere that doesn't conflict with something
56 * else. Put it above BOOTMAPSZ to eliminate conflicts.
58 * kernel_addr_r must be within the first 128M of RAM in order for the
59 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
60 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
61 * should not overlap that area, or the kernel will have to copy itself
62 * somewhere else before decompression. Similarly, the address of any other
63 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
64 * this up to 16M allows for a sizable kernel to be decompressed below the
65 * compressed load address.
67 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
68 * the compressed kernel to be up to 16M too.
70 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
71 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
73 #define MEM_LAYOUT_ENV_SETTINGS \
74 "scriptaddr=0x10000000\0" \
75 "kernel_addr_r=0x01000000\0" \
76 "fdt_addr_r=0x02000000\0" \
77 "ramdisk_addr_r=0x02100000\0"
80 #define CONFIG_SPL_TEXT_BASE 0x00108000
81 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000
82 #define CONFIG_SPL_STACK 0x000ffffc
84 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
86 /* Align LCD to 1MB boundary */
87 #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
89 #ifdef CONFIG_TEGRA_LP0
90 #define TEGRA_LP0_ADDR 0x1C406000
91 #define TEGRA_LP0_SIZE 0x2000
92 #define TEGRA_LP0_VEC \
93 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
94 "@" __stringify(TEGRA_LP0_ADDR) " "
100 * This parameter affects a TXFILLTUNING field that controls how much data is
101 * sent to the latency fifo before it is sent to the wire. Without this
102 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
103 * packets depending on the buffer address and size.
105 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10
106 #define CONFIG_EHCI_IS_TDI
108 /* Total I2C ports on Tegra20 */
109 #define TEGRA_I2C_NUM_CONTROLLERS 4
111 #define CONFIG_PARTITION_UUIDS
112 #define CONFIG_CMD_PART
114 #define CONFIG_SYS_NAND_SELF_INIT
115 #define CONFIG_SYS_NAND_ONFI_DETECTION
117 /* Misc utility code */
118 #define CONFIG_BOUNCE_BUFFER
120 #endif /* _TEGRA20_COMMON_H_ */