1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2012
4 * NVIDIA Corporation <www.nvidia.com>
7 #ifndef _TEGRA20_COMMON_H_
8 #define _TEGRA20_COMMON_H_
9 #include "tegra-common.h"
12 * NS16550 Configuration
14 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
17 * Miscellaneous configurable options
19 #define CONFIG_STACKBASE 0x02800000 /* 40MB */
21 /*-----------------------------------------------------------------------
26 * Memory layout for where various images get loaded by boot scripts:
28 * scriptaddr can be pretty much anywhere that doesn't conflict with something
29 * else. Put it above BOOTMAPSZ to eliminate conflicts.
31 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
32 * something else. Put it above BOOTMAPSZ to eliminate conflicts.
34 * kernel_addr_r must be within the first 128M of RAM in order for the
35 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
36 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
37 * should not overlap that area, or the kernel will have to copy itself
38 * somewhere else before decompression. Similarly, the address of any other
39 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
40 * this up to 16M allows for a sizable kernel to be decompressed below the
41 * compressed load address.
43 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
44 * the compressed kernel to be up to 16M too.
46 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
47 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
49 #define CONFIG_LOADADDR 0x01000000
50 #define MEM_LAYOUT_ENV_SETTINGS \
51 "scriptaddr=0x10000000\0" \
52 "pxefile_addr_r=0x10100000\0" \
53 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
54 "fdt_addr_r=0x02000000\0" \
55 "ramdisk_addr_r=0x02100000\0"
58 #define CONFIG_SPL_TEXT_BASE 0x00108000
59 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000
60 #define CONFIG_SPL_STACK 0x000ffffc
62 /* Align LCD to 1MB boundary */
63 #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
65 #ifdef CONFIG_TEGRA_LP0
66 #define TEGRA_LP0_ADDR 0x1C406000
67 #define TEGRA_LP0_SIZE 0x2000
68 #define TEGRA_LP0_VEC \
69 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
70 "@" __stringify(TEGRA_LP0_ADDR) " "
76 * This parameter affects a TXFILLTUNING field that controls how much data is
77 * sent to the latency fifo before it is sent to the wire. Without this
78 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
79 * packets depending on the buffer address and size.
81 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10
82 #define CONFIG_EHCI_IS_TDI
84 #define CONFIG_SYS_NAND_SELF_INIT
85 #define CONFIG_SYS_NAND_ONFI_DETECTION
87 #endif /* _TEGRA20_COMMON_H_ */