2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef _TEGRA20_COMMON_H_
25 #define _TEGRA20_COMMON_H_
26 #include "tegra-common.h"
29 * Errata configuration
31 #define CONFIG_ARM_ERRATA_742230
32 #define CONFIG_ARM_ERRATA_751472
35 * NS16550 Configuration
37 #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
40 * High Level Configuration Options
42 #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
44 /* Environment information, boards can override if required */
45 #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
48 * Miscellaneous configurable options
50 #define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
51 #define CONFIG_STACKBASE 0x02800000 /* 40MB */
53 /*-----------------------------------------------------------------------
56 #define CONFIG_SYS_TEXT_BASE 0x0010E000
59 * Memory layout for where various images get loaded by boot scripts:
61 * scriptaddr can be pretty much anywhere that doesn't conflict with something
62 * else. Put it above BOOTMAPSZ to eliminate conflicts.
64 * kernel_addr_r must be within the first 128M of RAM in order for the
65 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
66 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
67 * should not overlap that area, or the kernel will have to copy itself
68 * somewhere else before decompression. Similarly, the address of any other
69 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
70 * this up to 16M allows for a sizable kernel to be decompressed below the
71 * compressed load address.
73 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
74 * the compressed kernel to be up to 16M too.
76 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
77 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
79 #define MEM_LAYOUT_ENV_SETTINGS \
80 "scriptaddr=0x10000000\0" \
81 "kernel_addr_r=0x01000000\0" \
82 "fdt_addr_r=0x02000000\0" \
83 "ramdisk_addr_r=0x02100000\0"
86 #define CONFIG_SPL_TEXT_BASE 0x00108000
87 #define CONFIG_SYS_SPL_MALLOC_START 0x00090000
88 #define CONFIG_SPL_STACK 0x000ffffc
90 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
92 /* Align LCD to 1MB boundary */
93 #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
95 #ifdef CONFIG_TEGRA_LP0
96 #define TEGRA_LP0_ADDR 0x1C406000
97 #define TEGRA_LP0_SIZE 0x2000
98 #define TEGRA_LP0_VEC \
99 "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
100 "@" __stringify(TEGRA_LP0_ADDR) " "
102 #define TEGRA_LP0_VEC
106 * This parameter affects a TXFILLTUNING field that controls how much data is
107 * sent to the latency fifo before it is sent to the wire. Without this
108 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
109 * packets depending on the buffer address and size.
111 #define CONFIG_USB_EHCI_TXFIFO_THRESH 10
112 #define CONFIG_EHCI_IS_TDI
114 /* Total I2C ports on Tegra20 */
115 #define TEGRA_I2C_NUM_CONTROLLERS 4
117 #define CONFIG_SYS_NAND_SELF_INIT
118 #define CONFIG_SYS_NAND_ONFI_DETECTION
120 #endif /* _TEGRA20_COMMON_H_ */