2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_THEADORABLE_H
8 #define _CONFIG_THEADORABLE_H
11 * High Level Configuration Options (easy to change)
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
20 #define CONFIG_SYS_TEXT_BASE 0x00800000
21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
24 * Commands configuration
28 * The debugging version enables USB support via defconfig.
29 * This version should also enable all other non-production
30 * interfaces / features.
33 #define CONFIG_CMD_PCI
37 #define CONFIG_SYS_I2C
38 #define CONFIG_SYS_I2C_MVTWSI
39 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
40 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
41 #define CONFIG_SYS_I2C_SLAVE 0x0
42 #define CONFIG_SYS_I2C_SPEED 100000
44 /* USB/EHCI configuration */
45 #define CONFIG_EHCI_IS_TDI
46 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
48 /* SPI NOR flash default params, used by sf commands */
49 #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
50 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
52 /* Environment in SPI NOR flash */
53 #define CONFIG_ENV_IS_IN_SPI_FLASH
54 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
55 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
56 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
57 #define CONFIG_ENV_OVERWRITE
59 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
60 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
62 #define CONFIG_SYS_ALT_MEMTEST
63 #define CONFIG_PREBOOT
65 /* Keep device tree and initrd in lower memory so the kernel can access them */
66 #define CONFIG_EXTRA_ENV_SETTINGS \
67 "fdt_high=0x10000000\0" \
68 "initrd_high=0x10000000\0"
71 #define CONFIG_SYS_SATA_MAX_DEVICE 1
72 #define CONFIG_SATA_MV
76 /* Additional FS support/configuration */
77 #define CONFIG_SUPPORT_VFAT
81 #ifndef CONFIG_SPL_BUILD
82 #define CONFIG_PCI_MVEBU
86 /* Enable LCD and reserve 512KB from top of memory*/
87 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000
89 /* FPGA programming support */
91 #define CONFIG_FPGA_ALTERA
92 #define CONFIG_FPGA_STRATIX_V
97 #define CONFIG_BOOTCOUNT_LIMIT
98 #define CONFIG_BOOTCOUNT_RAM
99 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
100 #define BOOTCOUNT_ADDR 0x1000
103 * mv-common.h should be defined after CMD configs since it used them
104 * to enable certain macros
106 #include "mv-common.h"
109 * Memory layout while starting into the bin_hdr via the
112 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
113 * 0x4000.4030 bin_hdr start address
114 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
115 * 0x4007.fffc BootROM stack top
117 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
118 * L2 cache thus cannot be used.
122 /* Defines for SPL */
123 #define CONFIG_SPL_FRAMEWORK
124 #define CONFIG_SPL_TEXT_BASE 0x40004030
125 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
127 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
128 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
130 #ifdef CONFIG_SPL_BUILD
131 #define CONFIG_SYS_MALLOC_SIMPLE
134 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
135 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
137 /* SPL related SPI defines */
138 #define CONFIG_SPL_SPI_LOAD
139 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
140 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
142 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
143 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
145 #endif /* _CONFIG_THEADORABLE_H */