2 * (C) Copyright 2014, Cavium Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __THUNDERX_88XX_H__
8 #define __THUNDERX_88XX_H__
10 #define CONFIG_REMAKE_ELF
12 #define CONFIG_THUNDERX
14 #define CONFIG_SYS_64BIT
16 #define CONFIG_SYS_NO_FLASH
19 #define CONFIG_IDENT_STRING \
20 " for Cavium Thunder CN88XX ARM v8 Multi-Core"
21 #define CONFIG_BOOTP_VCI_STRING "Diagnostics"
23 #define MEM_BASE 0x00500000
25 #define CONFIG_COREID_MASK 0xffffff
27 #define CONFIG_SYS_FULL_VA
29 #define CONFIG_SYS_LOWMEM_BASE MEM_BASE
31 #define CONFIG_SYS_MEM_MAP {{0x000000000000UL, 0x40000000000UL, \
32 PTL2_MEMTYPE(MT_NORMAL) | \
33 PTL2_BLOCK_NON_SHARE}, \
34 {0x800000000000UL, 0x40000000000UL, \
35 PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \
36 PTL2_BLOCK_NON_SHARE}, \
37 {0x840000000000UL, 0x40000000000UL, \
38 PTL2_MEMTYPE(MT_DEVICE_NGNRNE) | \
39 PTL2_BLOCK_NON_SHARE}, \
42 #define CONFIG_SYS_MEM_MAP_SIZE 3
44 #define CONFIG_SYS_VA_BITS 48
45 #define CONFIG_SYS_PTL2_BITS 42
46 #define CONFIG_SYS_BLOCK_SHIFT 29
47 #define CONFIG_SYS_PTL1_ENTRIES 64
48 #define CONFIG_SYS_PTL2_ENTRIES 8192
50 #define CONFIG_SYS_PGTABLE_SIZE \
51 ((CONFIG_SYS_PTL1_ENTRIES + \
52 CONFIG_SYS_MEM_MAP_SIZE * CONFIG_SYS_PTL2_ENTRIES) * 8)
53 #define CONFIG_SYS_TCR_EL1_IPS_BITS (5UL << 32)
54 #define CONFIG_SYS_TCR_EL2_IPS_BITS (5 << 16)
55 #define CONFIG_SYS_TCR_EL3_IPS_BITS (5 << 16)
57 /* Link Definitions */
58 #define CONFIG_SYS_TEXT_BASE 0x00500000
59 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
61 /* SMP Spin Table Definitions */
62 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
65 /* Generic Timer Definitions */
66 #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
69 #define CONFIG_SYS_MEMTEST_START MEM_BASE
70 #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
72 /* Size of malloc() pool */
73 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
75 /* PL011 Serial Configuration */
77 #define CONFIG_PL01X_SERIAL
78 #define CONFIG_PL011_CLOCK 24000000
79 #define CONFIG_CONS_INDEX 1
81 /* Generic Interrupt Controller Definitions */
82 #define GICD_BASE (0x801000000000)
83 #define GICR_BASE (0x801000002000)
84 #define CONFIG_SYS_SERIAL0 0x87e024000000
85 #define CONFIG_SYS_SERIAL1 0x87e025000000
87 #define CONFIG_BAUDRATE 115200
89 /* Command line configuration */
93 #define CONFIG_BOOTP_BOOTFILESIZE
94 #define CONFIG_BOOTP_BOOTPATH
95 #define CONFIG_BOOTP_GATEWAY
96 #define CONFIG_BOOTP_HOSTNAME
97 #define CONFIG_BOOTP_PXE
98 #define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
100 /* Miscellaneous configurable options */
101 #define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
103 /* Physical Memory Map */
104 #define CONFIG_NR_DRAM_BANKS 1
105 #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
106 #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
107 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
109 /* Initial environment variables */
110 #define UBOOT_IMG_HEAD_SIZE 0x40
112 #define CONFIG_EXTRA_ENV_SETTINGS \
113 "kernel_addr=08007ffc0\0" \
114 "fdt_addr=0x94C00000\0" \
115 "fdt_high=0x9fffffff\0"
117 #define CONFIG_BOOTARGS \
118 "console=ttyAMA0,115200n8 " \
119 "earlycon=pl011,0x87e024000000 " \
120 "debug maxcpus=48 rootwait rw "\
121 "root=/dev/sda2 coherent_pool=16M"
122 #define CONFIG_BOOTDELAY 5
124 /* Do not preserve environment */
125 #define CONFIG_ENV_IS_NOWHERE 1
126 #define CONFIG_ENV_SIZE 0x1000
128 /* Monitor Command Prompt */
129 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
130 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
131 sizeof(CONFIG_SYS_PROMPT) + 16)
132 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
133 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
134 #define CONFIG_SYS_LONGHELP
135 #define CONFIG_CMDLINE_EDITING 1
136 #define CONFIG_SYS_MAXARGS 64 /* max command args */
137 #define CONFIG_NO_RELOCATION 1
138 #define CONFIG_LIB_RAND
139 #define PLL_REF_CLK 50000000 /* 50 MHz */
140 #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
142 #endif /* __THUNDERX_88XX_H__ */