4 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
5 * Antoine Tenart, <atenart@adeneo-embedded.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __CONFIG_TI816X_EVM_H
11 #define __CONFIG_TI816X_EVM_H
13 #include <configs/ti_armv7_omap.h>
14 #include <asm/arch/omap.h>
16 #define CONFIG_ENV_SIZE 0x2000
17 #define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
19 #define CONFIG_EXTRA_ENV_SETTINGS \
20 DEFAULT_LINUX_BOOT_ENV \
21 "mtdids=" MTDIDS_DEFAULT "\0" \
22 "mtdparts=" MTDPARTS_DEFAULT "\0" \
24 #define CONFIG_BOOTCOMMAND \
26 "fatload mmc 0 ${loadaddr} uImage;" \
29 #define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
32 #define V_OSCK 24000000 /* Clock output from T2 */
33 #define V_SCLK (V_OSCK >> 1)
35 #define CONFIG_CMD_ASKENV
37 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
38 #define CONFIG_SYS_SDRAM_BASE 0x80000000
41 * Platform/Board specific defs
43 #define CONFIG_SYS_CLK_FREQ 27000000
44 #define CONFIG_SYS_TIMERBASE 0x4802E000
45 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
48 * NS16550 Configuration
50 #define CONFIG_SYS_NS16550_SERIAL
51 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
52 #define CONFIG_SYS_NS16550_CLK (48000000)
53 #define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
55 /* allow overwriting serial config and ethaddr */
56 #define CONFIG_ENV_OVERWRITE
58 #define CONFIG_SERIAL1
59 #define CONFIG_SERIAL2
60 #define CONFIG_SERIAL3
61 #define CONFIG_CONS_INDEX 1
64 * GPMC NAND block. We support 1 device and the physical address to
65 * access CS0 at is 0x8000000.
67 #define CONFIG_SYS_NAND_BASE 0x8000000
68 #define CONFIG_SYS_MAX_NAND_DEVICE 1
70 /* NAND: SPL related configs */
71 #define CONFIG_SPL_NAND_AM33XX_BCH
73 /* NAND: device related configs */
74 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
75 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
76 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
77 CONFIG_SYS_NAND_PAGE_SIZE)
78 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
79 #define CONFIG_SYS_NAND_OOBSIZE 64
80 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
81 /* NAND: driver related configs */
82 #define CONFIG_NAND_OMAP_GPMC_PREFETCH
83 #define CONFIG_NAND_OMAP_ELM
84 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
85 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
86 10, 11, 12, 13, 14, 15, 16, 17, \
87 18, 19, 20, 21, 22, 23, 24, 25, \
88 26, 27, 28, 29, 30, 31, 32, 33, \
89 34, 35, 36, 37, 38, 39, 40, 41, \
90 42, 43, 44, 45, 46, 47, 48, 49, \
91 50, 51, 52, 53, 54, 55, 56, 57, }
93 #define CONFIG_SYS_NAND_ECCSIZE 512
94 #define CONFIG_SYS_NAND_ECCBYTES 14
95 #define CONFIG_SYS_NAND_ONFI_DETECTION
96 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
97 #define MTDIDS_DEFAULT "nand0=nand.0"
98 #define MTDPARTS_DEFAULT "mtdparts=nand.0:" \
100 "128k(NAND.SPL.backup1)," \
101 "128k(NAND.SPL.backup2)," \
102 "128k(NAND.SPL.backup3)," \
103 "256k(NAND.u-boot-spl-os)," \
105 "128k(NAND.u-boot-env)," \
106 "128k(NAND.u-boot-env.backup1)," \
108 "-(NAND.file-system)"
109 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
110 #define CONFIG_ENV_IS_IN_NAND
111 #define CONFIG_ENV_OFFSET 0x001c0000
112 #define CONFIG_ENV_OFFSET_REDUND 0x001e0000
113 #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
116 /* Defines for SPL */
117 #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
118 #define CONFIG_SPL_TEXT_BASE 0x40400000
119 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
120 CONFIG_SPL_TEXT_BASE)
122 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
124 #define CONFIG_SYS_TEXT_BASE 0x80800000
126 /* Since SPL did pll and ddr initialization for us,
127 * we don't need to do it twice.
129 #ifndef CONFIG_SPL_BUILD
130 #define CONFIG_SKIP_LOWLEVEL_INIT
134 * Disable MMC DM for SPL build and can be re-enabled after adding
137 #ifdef CONFIG_SPL_BUILD