4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 * SPDX-License-Identifier: GPL-2.0+
8 * For more details, please see the technical documents listed at
9 * http://www.ti.com/product/omap3530
10 * http://www.ti.com/product/omap3630
11 * http://www.ti.com/product/dm3730
14 #ifndef __CONFIG_TI_OMAP3_COMMON_H__
15 #define __CONFIG_TI_OMAP3_COMMON_H__
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/omap3.h>
21 /* The chip has SDRC controller */
25 #define V_OSCK 26000000 /* Clock output from T2 */
26 #define V_SCLK (V_OSCK >> 1)
28 /* NS16550 Configuration */
29 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
30 #define CONFIG_SYS_NS16550
31 #define CONFIG_SYS_NS16550_SERIAL
32 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
33 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
34 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
37 /* Select serial console configuration */
38 #define CONFIG_CONS_INDEX 3
39 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
40 #define CONFIG_SERIAL3 3
42 /* Physical Memory Map */
43 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
44 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
47 * OMAP3 has 12 GP timers, they can be driven by the system clock
48 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
49 * This rate is divided by a local divisor.
51 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
53 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
56 #define CONFIG_TWL4030_POWER 1
59 #define CONFIG_SPL_TEXT_BASE 0x40200800
60 #define CONFIG_SPL_MAX_SIZE (54 * 1024)
61 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
62 #define CONFIG_SPL_POWER_SUPPORT
63 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
68 #define CONFIG_SPL_NAND_SUPPORT
69 #define CONFIG_SPL_NAND_SIMPLE
70 #define CONFIG_SYS_NAND_BASE 0x30000000
73 /* Now bring in the rest of the common code. */
74 #include <configs/ti_armv7_common.h>
76 #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */