2 * (C) Copyright 2006-2008
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
8 * Corscience GmbH & Co. KG
9 * Thomas Weber <weber@corscience.de>
11 * Configuration settings for the Tricorder board.
13 * SPDX-License-Identifier: GPL-2.0+
19 /* High Level Configuration Options */
20 #define CONFIG_SYS_THUMB_BUILD
21 #define CONFIG_OMAP /* in a TI OMAP core */
22 #define CONFIG_OMAP_COMMON
23 /* Common ARM Erratas */
24 #define CONFIG_ARM_ERRATA_454179
25 #define CONFIG_ARM_ERRATA_430973
26 #define CONFIG_ARM_ERRATA_621766
28 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
30 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
31 * 64 bytes before this address should be set aside for u-boot.img's
32 * header. That is 0x800FFFC0--0x80100000 should not be used for any
35 #define CONFIG_SYS_TEXT_BASE 0x80100000
37 #define CONFIG_SDRC /* The chip has SDRC controller */
39 #include <asm/arch/cpu.h> /* get chip and board defs */
40 #include <asm/arch/omap.h>
42 #define CONFIG_SILENT_CONSOLE
45 #define V_OSCK 26000000 /* Clock output from T2 */
46 #define V_SCLK (V_OSCK >> 1)
48 #define CONFIG_MISC_INIT_R
50 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
51 #define CONFIG_SETUP_MEMORY_TAGS
52 #define CONFIG_INITRD_TAG
53 #define CONFIG_REVISION_TAG
55 /* Size of malloc() pool */
56 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
58 /* Hardware drivers */
61 #define CONFIG_OMAP_GPIO
64 #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 are in GPIO bank 2 */
67 #define CONFIG_STATUS_LED
68 #define CONFIG_BOARD_SPECIFIC_LED
69 #define CONFIG_CMD_LED /* LED command */
70 #define STATUS_LED_BIT (1 << 0)
71 #define STATUS_LED_STATE STATUS_LED_ON
72 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
73 #define STATUS_LED_BIT1 (1 << 1)
74 #define STATUS_LED_STATE1 STATUS_LED_ON
75 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
76 #define STATUS_LED_BIT2 (1 << 2)
77 #define STATUS_LED_STATE2 STATUS_LED_ON
78 #define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2)
80 /* NS16550 Configuration */
81 #define CONFIG_SYS_NS16550_SERIAL
82 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
83 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
85 /* select serial console configuration */
86 #define CONFIG_CONS_INDEX 3
87 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
88 #define CONFIG_SERIAL3 3
89 #define CONFIG_BAUDRATE 115200
90 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
94 #define CONFIG_GENERIC_MMC
96 #define CONFIG_OMAP_HSMMC
97 #define CONFIG_DOS_PARTITION
100 #define CONFIG_SYS_I2C
101 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
102 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
103 #define CONFIG_SYS_I2C_OMAP34XX
107 #define CONFIG_CMD_EEPROM
108 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
109 #define CONFIG_SYS_EEPROM_BUS_NUM 1
112 #define CONFIG_TWL4030_POWER
113 #define CONFIG_TWL4030_LED
115 /* Board NAND Info */
116 #define CONFIG_SYS_NO_FLASH /* no NOR flash */
117 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
118 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
119 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \
122 "384k(u-boot-env1)," \
124 "384k(u-boot-env2)," \
129 #define CONFIG_NAND_OMAP_GPMC
130 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
132 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
133 /* to access nand at */
135 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
138 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
139 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
141 /* commands to include */
142 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
143 #define CONFIG_CMD_NAND /* NAND support */
144 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
145 #define CONFIG_CMD_UBIFS /* UBIFS commands */
146 #define CONFIG_LZO /* LZO is needed for UBIFS */
148 #undef CONFIG_CMD_JFFS2 /* JFFS2 Support */
151 #define CONFIG_RBTREE
152 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
153 #define CONFIG_MTD_PARTITIONS
155 /* Environment information (this is the common part) */
158 /* hang() the board on panic() */
159 #define CONFIG_PANIC_HANG
161 /* environment placement (for NAND), is different for FLASHCARD but does not
163 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
164 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
165 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
166 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
168 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
169 * value can not be used here! */
170 #define CONFIG_LOADADDR 0x82000000
172 #define CONFIG_COMMON_ENV_SETTINGS \
173 "console=ttyO2,115200n8\0" \
176 "defaultdisplay=lcd\0" \
177 "kernelopts=mtdoops.mtddev=3\0" \
178 "mtdparts=" MTDPARTS_DEFAULT "\0" \
179 "mtdids=" MTDIDS_DEFAULT "\0" \
181 "setenv bootargs console=${console} " \
184 "vt.global_cursor_default=0 " \
186 "omapdss.def_disp=${defaultdisplay}\0"
188 #define CONFIG_BOOTCOMMAND "run autoboot"
190 /* specific environment settings for different use cases
191 * FLASHCARD: used to run a rdimage from sdcard to program the device
192 * 'NORMAL': used to boot kernel from sdcard, nand, ...
194 * The main aim for the FLASHCARD skin is to have an embedded environment
195 * which will not be influenced by any data already on the device.
197 #ifdef CONFIG_FLASHCARD
199 #define CONFIG_ENV_IS_NOWHERE
201 /* the rdaddr is 16 MiB before the loadaddr */
202 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
204 #define CONFIG_EXTRA_ENV_SETTINGS \
205 CONFIG_COMMON_ENV_SETTINGS \
209 "setenv bootargs ${bootargs} " \
210 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
211 "rdinit=/sbin/init; " \
212 "mmc dev ${mmcdev}; mmc rescan; " \
213 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
214 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
215 "bootm ${loadaddr} ${rdaddr}\0"
217 #else /* CONFIG_FLASHCARD */
219 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
221 #define CONFIG_ENV_IS_IN_NAND
223 #define CONFIG_EXTRA_ENV_SETTINGS \
224 CONFIG_COMMON_ENV_SETTINGS \
227 "setenv bootargs ${bootargs} " \
228 "root=/dev/mmcblk0p2 " \
233 "setenv bootargs ${bootargs} " \
236 "rootfstype=ubifs " \
238 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
239 "bootscript=echo Running bootscript from mmc ...; " \
240 "source ${loadaddr}\0" \
241 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
242 "mmcboot=echo Booting from mmc ...; " \
244 "bootm ${loadaddr}\0" \
245 "loaduimage_ubi=ubi part ubi; " \
246 "ubifsmount ubi:root; " \
247 "ubifsload ${loadaddr} /boot/uImage\0" \
248 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
249 "nandboot=echo Booting from nand ...; " \
251 "run loaduimage_nand; " \
252 "bootm ${loadaddr}\0" \
253 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
254 "if run loadbootscript; then " \
257 "if run loaduimage; then " \
259 "else run nandboot; " \
262 "else run nandboot; fi\0"
264 #endif /* CONFIG_FLASHCARD */
266 /* Miscellaneous configurable options */
267 #define CONFIG_SYS_LONGHELP /* undef to save memory */
268 #define CONFIG_CMDLINE_EDITING /* enable cmdline history */
269 #define CONFIG_AUTO_COMPLETE
270 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
271 /* Print Buffer Size */
272 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
273 sizeof(CONFIG_SYS_PROMPT) + 16)
274 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
276 /* Boot Argument Buffer Size */
277 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
279 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
280 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
281 0x07000000) /* 112 MB */
283 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
286 * OMAP3 has 12 GP timers, they can be driven by the system clock
287 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
288 * This rate is divided by a local divisor.
290 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
291 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
293 /* Physical Memory Map */
294 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
295 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
296 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
298 /* NAND and environment organization */
299 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
301 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
302 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
303 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
304 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
305 CONFIG_SYS_INIT_RAM_SIZE - \
306 GENERATED_GBL_DATA_SIZE)
309 #define CONFIG_SYS_SRAM_START 0x40200000
310 #define CONFIG_SYS_SRAM_SIZE 0x10000
312 /* Defines for SPL */
313 #define CONFIG_SPL_FRAMEWORK
314 #define CONFIG_SPL_NAND_SIMPLE
316 #define CONFIG_SPL_BOARD_INIT
317 #define CONFIG_SPL_NAND_BASE
318 #define CONFIG_SPL_NAND_DRIVERS
319 #define CONFIG_SPL_NAND_ECC
320 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
321 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
322 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
323 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
325 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
326 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
327 CONFIG_SPL_TEXT_BASE)
329 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
330 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
332 /* NAND boot config */
333 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
334 #define CONFIG_SYS_NAND_PAGE_COUNT 64
335 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
336 #define CONFIG_SYS_NAND_OOBSIZE 64
337 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
338 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
339 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
340 13, 14, 16, 17, 18, 19, 20, 21, 22, \
341 23, 24, 25, 26, 27, 28, 30, 31, 32, \
342 33, 34, 35, 36, 37, 38, 39, 40, 41, \
343 42, 44, 45, 46, 47, 48, 49, 50, 51, \
346 #define CONFIG_SYS_NAND_ECCSIZE 512
347 #define CONFIG_SYS_NAND_ECCBYTES 13
348 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
350 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
352 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
353 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
355 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
356 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
358 #define CONFIG_SYS_ALT_MEMTEST
359 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
360 #endif /* __CONFIG_H */