git.sur5r.net Git - u-boot/blob - include/configs/tricorder.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  *
   7  * (C) Copyright 2012
   8  * Corscience GmbH & Co. KG
   9  * Thomas Weber <weber@corscience.de>
  10  *
  11  * Configuration settings for the Tricorder board.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 #define CONFIG_MACH_TYPE                MACH_TYPE_TRICORDER
  20 /*
  21  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  22  * 64 bytes before this address should be set aside for u-boot.img's
  23  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  24  * other needs.
  25  */
  26 #define CONFIG_SYS_TEXT_BASE            0x80100000
  27
  28 #define CONFIG_SDRC                     /* The chip has SDRC controller */
  29
  30 #include <asm/arch/cpu.h>               /* get chip and board defs */
  31 #include <asm/arch/omap.h>
  32
  33 /* Clock Defines */
  34 #define V_OSCK                          26000000 /* Clock output from T2 */
  35 #define V_SCLK                          (V_OSCK >> 1)
  36
  37 #define CONFIG_MISC_INIT_R
  38
  39 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  40 #define CONFIG_SETUP_MEMORY_TAGS
  41 #define CONFIG_INITRD_TAG
  42 #define CONFIG_REVISION_TAG
  43
  44 /* Size of malloc() pool */
  45 #define CONFIG_SYS_MALLOC_LEN           (1024*1024)
  46
  47 /* Hardware drivers */
  48
  49 /* GPIO banks */
  50 #define CONFIG_OMAP3_GPIO_2             /* GPIO32..63 are in GPIO bank 2 */
  51
  52 /* LED support */
  53
  54 /* NS16550 Configuration */
  55 #define CONFIG_SYS_NS16550_SERIAL
  56 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  57 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
  58
  59 /* select serial console configuration */
  60 #define CONFIG_CONS_INDEX               3
  61 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  62 #define CONFIG_SERIAL3                  3
  63 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  64                                         115200}
  65
  66 /* I2C */
  67 #define CONFIG_SYS_I2C
  68 #define CONFIG_SYS_OMAP24_I2C_SPEED     100000
  69 #define CONFIG_SYS_OMAP24_I2C_SLAVE     1
  70 #define CONFIG_SYS_I2C_OMAP34XX
  71
  72
  73 /* EEPROM */
  74 #define CONFIG_CMD_EEPROM
  75 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
  76 #define CONFIG_SYS_EEPROM_BUS_NUM       1
  77
  78 /* TWL4030 */
  79 #define CONFIG_TWL4030_LED
  80
  81 /* Board NAND Info */
  82 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
  83 #define MTDIDS_DEFAULT                  "nand0=omap2-nand.0"
  84 #define MTDPARTS_DEFAULT                "mtdparts=omap2-nand.0:" \
  85                                                 "128k(SPL)," \
  86                                                 "1m(u-boot)," \
  87                                                 "384k(u-boot-env1)," \
  88                                                 "1152k(mtdoops)," \
  89                                                 "384k(u-boot-env2)," \
  90                                                 "5m(kernel)," \
  91                                                 "2m(fdt)," \
  92                                                 "-(ubi)"
  93
  94 #define CONFIG_NAND_OMAP_GPMC
  95 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
  96                                                         /* to access nand */
  97 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  98                                                         /* to access nand at */
  99                                                         /* CS0 */
 100 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 101                                                         /* devices */
 102 #define CONFIG_BCH
 103 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 104 #define CONFIG_SYS_NAND_MAX_ECCPOS      56
 105
 106 /* commands to include */
 107 #define CONFIG_CMD_MTDPARTS             /* Enable MTD parts commands */
 108 #define CONFIG_CMD_NAND                 /* NAND support */
 109 #define CONFIG_CMD_NAND_LOCK_UNLOCK     /* nand (un)lock commands */
 110 #define CONFIG_CMD_UBIFS                /* UBIFS commands */
 111 #define CONFIG_LZO                      /* LZO is needed for UBIFS */
 112
 113 #undef CONFIG_CMD_JFFS2                 /* JFFS2 Support */
 114
 115 /* needed for ubi */
 116 #define CONFIG_RBTREE
 117 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
 118 #define CONFIG_MTD_PARTITIONS
 119
 120 /* Environment information (this is the common part) */
 121
 122
 123 /* hang() the board on panic() */
 124 #define CONFIG_PANIC_HANG
 125
 126 /* environment placement (for NAND), is different for FLASHCARD but does not
 127  * harm there */
 128 #define CONFIG_ENV_OFFSET               0x120000    /* env start */
 129 #define CONFIG_ENV_OFFSET_REDUND        0x2A0000    /* redundant env start */
 130 #define CONFIG_ENV_SIZE                 (16 << 10)  /* use 16KiB for env */
 131 #define CONFIG_ENV_RANGE                (384 << 10) /* allow badblocks in env */
 132
 133 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
 134  * value can not be used here! */
 135 #define CONFIG_LOADADDR         0x82000000
 136
 137 #define CONFIG_COMMON_ENV_SETTINGS \
 138         "console=ttyO2,115200n8\0" \
 139         "mmcdev=0\0" \
 140         "vram=3M\0" \
 141         "defaultdisplay=lcd\0" \
 142         "kernelopts=mtdoops.mtddev=3\0" \
 143         "mtdparts=" MTDPARTS_DEFAULT "\0" \
 144         "mtdids=" MTDIDS_DEFAULT "\0" \
 145         "commonargs=" \
 146                 "setenv bootargs console=${console} " \
 147                 "${mtdparts} " \
 148                 "${kernelopts} " \
 149                 "vt.global_cursor_default=0 " \
 150                 "vram=${vram} " \
 151                 "omapdss.def_disp=${defaultdisplay}\0"
 152
 153 #define CONFIG_BOOTCOMMAND "run autoboot"
 154
 155 /* specific environment settings for different use cases
 156  * FLASHCARD: used to run a rdimage from sdcard to program the device
 157  * 'NORMAL': used to boot kernel from sdcard, nand, ...
 158  *
 159  * The main aim for the FLASHCARD skin is to have an embedded environment
 160  * which will not be influenced by any data already on the device.
 161  */
 162 #ifdef CONFIG_FLASHCARD
 163
 164 #define CONFIG_ENV_IS_NOWHERE
 165
 166 /* the rdaddr is 16 MiB before the loadaddr */
 167 #define CONFIG_ENV_RDADDR       "rdaddr=0x81000000\0"
 168
 169 #define CONFIG_EXTRA_ENV_SETTINGS \
 170         CONFIG_COMMON_ENV_SETTINGS \
 171         CONFIG_ENV_RDADDR \
 172         "autoboot=" \
 173         "run commonargs; " \
 174         "setenv bootargs ${bootargs} " \
 175                 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
 176                 "rdinit=/sbin/init; " \
 177         "mmc dev ${mmcdev}; mmc rescan; " \
 178         "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
 179         "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
 180         "bootm ${loadaddr} ${rdaddr}\0"
 181
 182 #else /* CONFIG_FLASHCARD */
 183
 184 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
 185
 186 #define CONFIG_ENV_IS_IN_NAND
 187
 188 #define CONFIG_EXTRA_ENV_SETTINGS \
 189         CONFIG_COMMON_ENV_SETTINGS \
 190         "mmcargs=" \
 191                 "run commonargs; " \
 192                 "setenv bootargs ${bootargs} " \
 193                 "root=/dev/mmcblk0p2 " \
 194                 "rootwait " \
 195                 "rw\0" \
 196         "nandargs=" \
 197                 "run commonargs; " \
 198                 "setenv bootargs ${bootargs} " \
 199                 "root=ubi0:root " \
 200                 "ubi.mtd=7 " \
 201                 "rootfstype=ubifs " \
 202                 "ro\0" \
 203         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 204         "bootscript=echo Running bootscript from mmc ...; " \
 205                 "source ${loadaddr}\0" \
 206         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 207         "mmcboot=echo Booting from mmc ...; " \
 208                 "run mmcargs; " \
 209                 "bootm ${loadaddr}\0" \
 210         "loaduimage_ubi=ubi part ubi; " \
 211                 "ubifsmount ubi:root; " \
 212                 "ubifsload ${loadaddr} /boot/uImage\0" \
 213         "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
 214         "nandboot=echo Booting from nand ...; " \
 215                 "run nandargs; " \
 216                 "run loaduimage_nand; " \
 217                 "bootm ${loadaddr}\0" \
 218         "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 219                         "if run loadbootscript; then " \
 220                                 "run bootscript; " \
 221                         "else " \
 222                                 "if run loaduimage; then " \
 223                                         "run mmcboot; " \
 224                                 "else run nandboot; " \
 225                                 "fi; " \
 226                         "fi; " \
 227                 "else run nandboot; fi\0"
 228
 229 #endif /* CONFIG_FLASHCARD */
 230
 231 /* Miscellaneous configurable options */
 232 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 233 #define CONFIG_CMDLINE_EDITING          /* enable cmdline history */
 234 #define CONFIG_AUTO_COMPLETE
 235 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 236 /* Print Buffer Size */
 237 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 238                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 239 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 240
 241 /* Boot Argument Buffer Size */
 242 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 243
 244 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x00000000)
 245 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 246                                         0x07000000) /* 112 MB */
 247
 248 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0 + 0x02000000)
 249
 250 /*
 251  * OMAP3 has 12 GP timers, they can be driven by the system clock
 252  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 253  * This rate is divided by a local divisor.
 254  */
 255 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 256 #define CONFIG_SYS_PTV                  2 /* Divisor: 2^(PTV+1) => 8 */
 257
 258 /*  Physical Memory Map  */
 259 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
 260 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
 261 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
 262
 263 /* NAND and environment organization  */
 264 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 265
 266 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 267 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 268 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 269 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 270                                                 CONFIG_SYS_INIT_RAM_SIZE - \
 271                                                 GENERATED_GBL_DATA_SIZE)
 272
 273 /* SRAM config */
 274 #define CONFIG_SYS_SRAM_START           0x40200000
 275 #define CONFIG_SYS_SRAM_SIZE            0x10000
 276
 277 /* Defines for SPL */
 278 #define CONFIG_SPL_FRAMEWORK
 279 #define CONFIG_SPL_NAND_SIMPLE
 280
 281 #define CONFIG_SPL_BOARD_INIT
 282 #define CONFIG_SPL_NAND_BASE
 283 #define CONFIG_SPL_NAND_DRIVERS
 284 #define CONFIG_SPL_NAND_ECC
 285 #define CONFIG_SPL_LDSCRIPT             "arch/arm/mach-omap2/u-boot-spl.lds"
 286 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"
 287 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 288
 289 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
 290 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 291                                          CONFIG_SPL_TEXT_BASE)
 292
 293 #define CONFIG_SPL_BSS_START_ADDR       0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
 294 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 295
 296 /* NAND boot config */
 297 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 298 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 299 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 300 #define CONFIG_SYS_NAND_OOBSIZE         64
 301 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 302 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 303 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
 304                                          13, 14, 16, 17, 18, 19, 20, 21, 22, \
 305                                          23, 24, 25, 26, 27, 28, 30, 31, 32, \
 306                                          33, 34, 35, 36, 37, 38, 39, 40, 41, \
 307                                          42, 44, 45, 46, 47, 48, 49, 50, 51, \
 308                                          52, 53, 54, 55, 56}
 309
 310 #define CONFIG_SYS_NAND_ECCSIZE         512
 311 #define CONFIG_SYS_NAND_ECCBYTES        13
 312 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 313
 314 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 315
 316 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x20000
 317 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x100000
 318
 319 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 320 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
 321
 322 #define CONFIG_SYS_ALT_MEMTEST
 323 #define CONFIG_SYS_MEMTEST_SCRATCH      0x81000000
 324 #endif /* __CONFIG_H */