2 * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
3 * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
5 * Configuration settings for the HALE TT-01 board.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/imx-regs.h>
31 /* High Level Configuration Options */
32 #define CONFIG_ARM1136
34 #define CONFIG_MX31_HCLK_FREQ 26000000
35 #define CONFIG_MX31_CLK32 32768
37 #define CONFIG_DISPLAY_CPUINFO
38 #define CONFIG_DISPLAY_BOARDINFO
40 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
41 #define CONFIG_SETUP_MEMORY_TAGS
42 #define CONFIG_INITRD_TAG
44 #define CONFIG_MACH_TYPE 3726 /* not yet in mach-types.h */
45 #define CONFIG_SYS_TEXT_BASE 0xA0000000
49 * Physical Memory Map:
50 * CS settings are defined by i.MX31:
51 * - CSD0 and CDS1 are 256MB each, starting at 0x80000000 and 0x9000000
52 * - CS0 and CS1 are 128MB each, at A0000000 and A8000000
53 * - CS2 to CS5 are 32MB each, at B0.., B2.., B4.., B6..
55 * HALE set-up of the bluetechnix board for now is:
56 * - 128MB DDR (2x64MB, 2x16bit), connected to 32bit DDR ram interface
57 * - NOR-Flash (Spansion 32MB MCP, Flash+16MB PSRAM), 16bit interface at CS0
58 * - S71WS256ND0BFWYM (and CS1 for 64MB S71WS512ND0 without PSRAM)
59 * the flash chip is a mirrorbit S29WS256N !
60 * - the PSRAM is hooked to CS5 (0xB6000000)
61 * - Intel Strata Flash PF48F2000P0ZB00, 16bit interface at (CS0 or) CS1
62 * - 64Mbit = 8MByte (will go away in the production set-up)
63 * - NAND-Flash NAND01GR3B2BZA6 at NAND-FC:
64 * 1Gbit=128MB, 2048+64 bytes/page, 64pages x 1024 blocks
65 * - Ethernet controller SMC9118 at CS4 via FPGA, 16bit interface
67 * u-boot will support the 32MB nor flash and the 128MB NAND flash, the PSRAM
68 * is not used right now. We should be able to reduce the SOM to NAND flash
69 * only and boot from there.
71 #define CONFIG_NR_DRAM_BANKS 1
72 #define PHYS_SDRAM_1 CSD0_BASE
73 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
75 #define CONFIG_BOARD_EARLY_INIT_F
76 #define CONFIG_BOARD_LATE_INIT
78 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
79 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
80 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
81 #define CONFIG_SYS_GBL_DATA_OFFSET \
82 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
83 #define CONFIG_SYS_INIT_SP_ADDR \
84 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
86 /* default load address, 1MB up the road */
87 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1+0x100000)
89 /* Size of malloc() pool, make sure possible frame buffer fits */
90 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 10*1024*1024)
92 /* memtest works on all but the last 1MB (u-boot) and malloc area */
93 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
94 #define CONFIG_SYS_MEMTEST_END \
95 (PHYS_SDRAM_1+(PHYS_SDRAM_1_SIZE-CONFIG_SYS_MALLOC_LEN-0x100000))
97 /* CFI FLASH driver setup */
98 #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
99 #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
100 #define CONFIG_FLASH_SPANSION_S29WS_N
102 * TODO: Bluetechnix (the supplier of the SOM) did define these values
103 * in their original version of u-boot (1.2 or so). This should be
106 * #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
107 * #define CONFIG_SYS_FLASH_PROTECTION
109 #define CONFIG_SYS_FLASH_BASE CS0_BASE
110 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
111 #define CONFIG_SYS_MAX_FLASH_SECT (254+8) /* max number of sectors per chip */
114 * FLASH and environment organization, only the Spansion chip is supported:
115 * - it has 254 * 128kB + 8 * 32kB blocks
116 * - this setup uses 4*32k+3*128k as monitor space = 0xA000 0000 to 0xA00F FFFF
117 * and 2 sectors with 128k as environment =
118 * A010 0000 to 0xA011 FFFF and 0xA012 0000 to 0xA013 FFFF
119 * - this could be less, but this is only for developer versions of the board
120 * and no-one is going to use the NOR flash anyway.
122 * Monitor is at the beginning of the NOR-Flash, 1MB reserved. Again this is
123 * way to large, but it avoids ENV overwrite (when updating u-boot) in case
124 * size breaks the next boundary (as it has with 128k).
126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
127 #define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
129 #define CONFIG_ENV_IS_IN_FLASH
130 #define CONFIG_ENV_SECT_SIZE (128 * 1024)
131 #define CONFIG_ENV_SIZE (128 * 1024)
133 /* Address and size of Redundant Environment Sector */
134 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
135 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
137 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
139 /* Hardware drivers */
142 * on TT-01 UART1 pins are used by Audio, so we use UART2
143 * TT-01 implements a hardware that turns off components depending on
144 * the power level. In PL=1 the RS232 transceiver is usually off,
145 * make sure that the transceiver is enabled during PL=1 for testing!
147 #define CONFIG_MXC_UART
148 #define CONFIG_MXC_UART_BASE UART2_BASE
150 #define CONFIG_MXC_SPI
151 #define CONFIG_MXC_GPIO
153 /* MC13783 connected to CSPI3 and SS0 */
155 #define CONFIG_PMIC_SPI
156 #define CONFIG_PMIC_FSL
158 #define CONFIG_FSL_PMIC_BUS 2
159 #define CONFIG_FSL_PMIC_CS 0
160 #define CONFIG_FSL_PMIC_CLK 1000000
161 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
162 #define CONFIG_FSL_PMIC_BITLEN 32
164 #define CONFIG_RTC_MC13XXX
166 /* allow to overwrite serial and ethaddr */
167 #define CONFIG_ENV_OVERWRITE
168 /* console is UART2 on TT-01 */
169 #define CONFIG_CONS_INDEX 1
170 #define CONFIG_BAUDRATE 115200
172 /* ethernet setup for the onboard smc9118 */
174 #define CONFIG_SMC911X
175 /* 16 bit, onboard ethernet, decoded via MACH-MX0 FPGA at 0x84200000 */
176 #define CONFIG_SMC911X_BASE (CS4_BASE+0x200000)
177 #define CONFIG_SMC911X_16_BIT
181 #define CONFIG_GENERIC_MMC
182 #define CONFIG_MXC_MMC
183 #define CONFIG_MXC_MCI_REGS_BASE SDHC1_BASE_ADDR
187 #define CONFIG_VIDEO_MX3
188 #define CONFIG_CFB_CONSOLE
189 #define CONFIG_VIDEO_LOGO
190 /* splash image won't work with NAND boot, use preboot script */
191 #define CONFIG_VIDEO_SW_CURSOR
192 #define CONFIG_CONSOLE_EXTRA_INFO /* display additional board info */
193 #define CONFIG_VGA_AS_SINGLE_DEVICE /* display is an output only device */
195 /* allow stdin, stdout and stderr variables to redirect output */
196 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
197 #define CONFIG_SILENT_CONSOLE /* UARTs used externally (release) */
198 #define CONFIG_SYS_DEVICE_NULLDEV /* allow console to be turned off */
199 #define CONFIG_PREBOOT
201 /* allow decompressing max. 4MB */
202 #define CONFIG_VIDEO_BMP_GZIP
203 /* this is not only used by cfb_console.c for the logo, but also in cmd_bmp.c */
204 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4*1024*1024)
210 #include <config_cmd_default.h>
212 #define CONFIG_CMD_DATE
213 #define CONFIG_CMD_PING
214 #define CONFIG_CMD_DHCP
215 #define CONFIG_CMD_SAVEENV
216 #define CONFIG_CMD_NAND
218 * #define CONFIG_CMD_NAND_LOCK_UNLOCK the NAND01... chip does not support
219 * the NAND_CMD_LOCK_STATUS command, however the NFC of i.MX31 supports
220 * a software locking scheme.
222 #define CONFIG_CMD_BMP
224 #define CONFIG_BOOTDELAY 3
227 * currently a default setting for booting via script is implemented
228 * set user to login name and serverip to tftp host, define your
229 * boot behaviour in bootscript.loginname
231 * TT-01 board specific TFT setup (used by drivers/video/mx3fb.c)
233 * This set-up is for the L5F30947T04 by Epson, which is
234 * 800x480, 33MHz pixel clock, 60Hz vsync, 31.6kHz hsync
235 * sync must be set to: DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL
237 #define CONFIG_EXTRA_ENV_SETTINGS \
238 "videomode=epson\0" \
239 "epson=video=ctfb:x:800,y:480,depth:16,mode:0,pclk:30076," \
240 "le:215,ri:1,up:32,lo:13,hs:7,vs:10,sync:100663296,vmode:0\0" \
241 "bootcmd=dhcp bootscript.${user}; source\0"
243 #define CONFIG_BOOTP_SERVERIP /* tftp serverip not overruled by dhcp server */
244 #define CONFIG_BOOTP_SEND_HOSTNAME /* if env-var 'hostname' is set, send it */
246 /* Miscellaneous configurable options */
247 #define CONFIG_SYS_HUSH_PARSER
249 #define CONFIG_SYS_LONGHELP /* undef to save memory */
250 #define CONFIG_SYS_PROMPT "TT01> "
251 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
252 /* Print Buffer Size */
253 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
254 sizeof(CONFIG_SYS_PROMPT)+16)
255 /* max number of command args */
256 #define CONFIG_SYS_MAXARGS 16
257 /* Boot Argument Buffer Size */
258 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
260 #define CONFIG_SYS_HZ 1000
262 #define CONFIG_CMDLINE_EDITING
264 /* MMC boot support */
265 #define CONFIG_CMD_MMC
266 #define CONFIG_DOS_PARTITION
267 #define CONFIG_EFI_PARTITION
268 #define CONFIG_CMD_EXT2
269 #define CONFIG_CMD_FAT
271 #define CONFIG_NAND_MXC
272 #define CONFIG_SYS_MAX_NAND_DEVICE 1
275 * actually this is nothing someone wants to configure!
276 * CONFIG_SYS_NAND_BASE despite being passed to board_nand_init()
277 * is not used by the driver.
279 #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
280 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
281 #define CONFIG_MXC_NAND_HWECC
283 /* the current u-boot driver does not use the nand flash setup! */
284 #define CONFIG_SYS_NAND_LARGEPAGE
287 * #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
288 * the current u-boot mxc_nand.c tries to auto-detect, but this only
289 * reads the boot settings during reset (which might be wrong)
292 #endif /* __CONFIG_H */