2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_MPC860 1
37 #define CONFIG_MPC860T 1
38 #define CONFIG_MPC862 1 /* enable 862 since the */
39 #define CONFIG_MPC857 1 /* 857 is a variant of the 862 */
41 #define CONFIG_UC100 1 /* ...on a UC100 module */
43 #define MPC8XX_FACT 4 /* Multiply by 4 */
44 #define MPC8XX_XIN 25000000 /* 25.0 MHz in */
45 #define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
46 /* define if cant' use get_gclk_freq */
48 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
49 #undef CONFIG_8xx_CONS_SMC2
50 #undef CONFIG_8xx_CONS_NONE
52 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
54 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
56 #define CONFIG_BOOTCOUNT_LIMIT
58 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60 #define CONFIG_BOARD_TYPES 1 /* support board types */
62 #define CONFIG_PREBOOT "echo;" \
63 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
66 #undef CONFIG_BOOTARGS
68 #define CONFIG_EXTRA_ENV_SETTINGS \
70 "nfsargs=setenv bootargs root=/dev/nfs rw " \
71 "nfsroot=${serverip}:${rootpath}\0" \
72 "ramargs=setenv bootargs root=/dev/ram rw\0" \
73 "addip=setenv bootargs ${bootargs} " \
74 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
75 ":${hostname}:${netdev}:off panic=1\0" \
76 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
77 "flash_nfs=run nfsargs addip addtty;" \
78 "bootm ${kernel_addr}\0" \
79 "flash_self=run ramargs addip addtty;" \
80 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
83 "rootpath=/opt/eldk/ppc_8xx\0" \
84 "bootfile=/tftpboot/uc100/uImage\0" \
85 "kernel_addr=40000000\0" \
86 "ramdisk_addr=40100000\0" \
87 "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \
88 "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \
89 "cp.b 100000 40700000 ${filesize};" \
90 "setenv filesize;saveenv\0" \
92 #define CONFIG_BOOTCOMMAND "run flash_self"
94 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
95 #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
97 #undef CONFIG_WATCHDOG /* watchdog disabled */
99 #undef CONFIG_STATUS_LED /* no status-led */
101 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
103 #define CONFIG_MAC_PARTITION
104 #define CONFIG_DOS_PARTITION
106 #undef CONFIG_RTC_MPC8xx
107 #define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
108 #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
111 * Power On Self Test support
113 #define CONFIG_POST ( CFG_POST_CACHE | \
121 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
123 #define CFG_CMD_POST_DIAG 0
128 * Command line configuration.
130 #include <config_cmd_default.h>
132 #define CONFIG_CMD_ASKENV
133 #define CONFIG_CMD_DATE
134 #define CONFIG_CMD_DHCP
135 #define CONFIG_CMD_EEPROM
136 #define CONFIG_CMD_ELF
137 #define CONFIG_CMD_FAT
138 #define CONFIG_CMD_I2C
139 #define CONFIG_CMD_IDE
140 #define CONFIG_CMD_MII
141 #define CONFIG_CMD_NFS
142 #define CONFIG_CMD_PING
143 #define CONFIG_CMD_POST
144 #define CONFIG_CMD_SNTP
147 #define CONFIG_NETCONSOLE
150 * Miscellaneous configurable options
152 #define CFG_LONGHELP /* undef to save memory */
153 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
156 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
158 #ifdef CFG_HUSH_PARSER
159 #define CFG_PROMPT_HUSH_PS2 "> "
162 #if defined(CONFIG_CMD_KGDB)
163 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
165 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
167 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
168 #define CFG_MAXARGS 16 /* max number of command args */
169 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
171 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
172 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
174 #define CFG_LOAD_ADDR 0x100000 /* default load address */
176 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
178 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
180 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
183 * Low Level Configuration Settings
184 * (address mappings, register initial values, etc.)
185 * You should know what you are doing if you make changes here.
187 /*-----------------------------------------------------------------------
188 * Internal Memory Mapped Register
190 #define CFG_IMMR 0xF0000000
192 /*-----------------------------------------------------------------------
193 * Definitions for initial stack pointer and data area (in DPRAM)
195 #define CFG_INIT_RAM_ADDR CFG_IMMR
196 #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
197 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
198 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
199 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
201 /*-----------------------------------------------------------------------
202 * Start addresses for the final memory configuration
203 * (Set up by the startup code)
204 * Please note that CFG_SDRAM_BASE _must_ start at 0
206 #define CFG_SDRAM_BASE 0x00000000
207 #define CFG_FLASH_BASE 0x40000000
208 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
209 #define CFG_MONITOR_BASE (CFG_FLASH_BASE+0x00700000) /* resetvec fff00100*/
210 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
212 /*-----------------------------------------------------------------------
213 * Address accessed to reset the board - must not be mapped/assigned
215 #define CFG_RESET_ADDRESS 0x90000000
218 * For booting Linux, the board info and command line data
219 * have to be in the first 8 MB of memory, since this is
220 * the maximum mapped by the Linux kernel during initialization.
222 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
224 /*-----------------------------------------------------------------------
227 #define CFG_FLASH_CFI /* The flash is CFI compatible */
228 #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
229 #define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
231 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
232 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
234 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
235 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
237 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
239 #define CFG_ENV_IS_IN_FLASH 1
240 #define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
241 #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
242 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
244 /* Address and size of Redundant Environment Sector */
245 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
246 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
248 /*-----------------------------------------------------------------------
249 * Cache Configuration
251 #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
252 #if defined(CONFIG_CMD_KGDB)
253 #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
256 /*-----------------------------------------------------------------------
257 * SYPCR - System Protection Control 11-9
258 * SYPCR can only be written once after reset!
259 *-----------------------------------------------------------------------
260 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
262 #if defined(CONFIG_WATCHDOG)
263 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
264 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
266 #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
269 /*-----------------------------------------------------------------------
270 * SIUMCR - SIU Module Configuration 11-6
271 *-----------------------------------------------------------------------
272 * PCMCIA config., multi-function pin tri-state
274 #define CFG_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
276 /*-----------------------------------------------------------------------
277 * TBSCR - Time Base Status and Control 11-26
278 *-----------------------------------------------------------------------
279 * Clear Reference Interrupt Status, Timebase freezing enabled
281 #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
283 /*-----------------------------------------------------------------------
284 * RTCSC - Real-Time Clock Status and Control Register 11-27
285 *-----------------------------------------------------------------------
287 #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
289 /*-----------------------------------------------------------------------
290 * PISCR - Periodic Interrupt Status and Control 11-31
291 *-----------------------------------------------------------------------
292 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
294 #define CFG_PISCR (PISCR_PS | PISCR_PITF)
296 /*-----------------------------------------------------------------------
297 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
298 *-----------------------------------------------------------------------
299 * Reset PLL lock status sticky bit, timer expired status bit and timer
300 * interrupt status bit
302 #define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
303 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
305 /*-----------------------------------------------------------------------
306 * SCCR - System Clock and reset Control Register 15-27
307 *-----------------------------------------------------------------------
308 * Set clock output, timebase and RTC source and divider,
309 * power management and some other internal clocks
311 #define SCCR_MASK 0x00000000
312 #define CFG_SCCR (SCCR_EBDF11)
314 /*-----------------------------------------------------------------------
316 *-----------------------------------------------------------------------
319 #define CFG_PCMCIA_MEM_ADDR (0xE0000000)
320 #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
321 #define CFG_PCMCIA_DMA_ADDR (0xE4000000)
322 #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
323 #define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
324 #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
325 #define CFG_PCMCIA_IO_ADDR (0xEC000000)
326 #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
328 /*-----------------------------------------------------------------------
329 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
330 *-----------------------------------------------------------------------
333 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
335 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
336 #undef CONFIG_IDE_LED /* LED for ide not supported */
337 #undef CONFIG_IDE_RESET /* reset for ide not supported */
339 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
340 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
342 #define CFG_ATA_IDE0_OFFSET 0x0000
344 #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
346 /* Offset for data I/O */
347 #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
349 /* Offset for normal register accesses */
350 #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
352 /* Offset for alternate registers */
353 #define CFG_ATA_ALT_OFFSET 0x0100
355 /*-----------------------------------------------------------------------
357 *-----------------------------------------------------------------------
363 * Init Memory Controller:
365 * BR0/1 and OR0/1 (FLASH)
368 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
369 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
371 /* used to re-map FLASH both when starting from SRAM or FLASH:
372 * restrict access enough to keep SRAM working (if any)
373 * but not too much to meddle with FLASH accesses
375 #define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
376 #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
381 #define CFG_OR_TIMING_FLASH (0x00000d24)
383 #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
384 #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
385 #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
387 #define CFG_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
388 #define CFG_OR1_PRELIM 0xfc000a00
389 #define CFG_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
390 #define CFG_OR2_PRELIM 0xfff00d24
391 #define CFG_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
392 #define CFG_OR3_PRELIM 0xffff8f44
393 #define CFG_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
394 #define CFG_OR4_PRELIM 0xffff0300
395 #define CFG_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
396 #define CFG_OR5_PRELIM 0xffff8db0
399 * Memory Periodic Timer Prescaler
401 * The Divider for PTA (refresh timer) configuration is based on an
402 * example SDRAM configuration (64 MBit, one bank). The adjustment to
403 * the number of chip selects (NCS) and the actually needed refresh
404 * rate is done by setting MPTPR.
406 * PTA is calculated from
407 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
409 * gclk CPU clock (not bus clock!)
410 * Trefresh Refresh cycle * 4 (four word bursts used)
412 * 4096 Rows from SDRAM example configuration
413 * 1000 factor s -> ms
414 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
415 * 4 Number of refresh cycles per period
416 * 64 Refresh cycle in ms per number of rows
417 * --------------------------------------------
418 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
420 * 50 MHz => 50.000.000 / Divider = 98
421 * 66 Mhz => 66.000.000 / Divider = 129
422 * 80 Mhz => 80.000.000 / Divider = 156
423 * 100 Mhz => 100.000.000 / Divider = 195
426 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
427 #define CFG_MAMR_PTA 98
430 * For 16 MBit, refresh rates could be 31.3 us
431 * (= 64 ms / 2K = 125 / quad bursts).
432 * For a simpler initialization, 15.6 us is used instead.
434 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
435 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
437 #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
438 #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
440 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
441 #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
442 #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
445 * MAMR settings for SDRAM
449 #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
450 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
451 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
453 #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
454 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
455 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
457 #define CFG_MAMR_VAL 0x30904114 /* for SDRAM */
458 #define CFG_MBMR_VAL 0xff001111 /* for Interbus-MPM */
460 /*-----------------------------------------------------------------------
464 /* enable I2C and select the hardware/software driver */
465 #undef CONFIG_HARD_I2C /* I2C with hardware support */
466 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
468 #define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
469 #define CFG_I2C_SLAVE 0xFE
471 #ifdef CONFIG_SOFT_I2C
473 * Software (bit-bang) I2C driver configuration
475 #define PB_SCL 0x00000020 /* PB 26 */
476 #define PB_SDA 0x00000010 /* PB 27 */
478 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
479 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
480 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
481 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
482 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
483 else immr->im_cpm.cp_pbdat &= ~PB_SDA
484 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
485 else immr->im_cpm.cp_pbdat &= ~PB_SCL
486 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
487 #endif /* CONFIG_SOFT_I2C */
489 /*-----------------------------------------------------------------------
490 * I2C EEPROM (24C164)
492 #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
493 #define CFG_I2C_EEPROM_ADDR_LEN 1
494 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
495 #define CFG_EEPROM_PAGE_WRITE_BITS 4
498 * Internal Definitions
502 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
503 #define BOOTFLAG_WARM 0x02 /* Software reboot */
505 #define CONFIG_FEC_ENET 1 /* use FEC ethernet */
508 #define CFG_DISCOVER_PHY 1
510 #endif /* __CONFIG_H */