git.sur5r.net Git - u-boot/blob - include/configs/uniphier.h

   1 /*
   2  * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /* U-Boot - Common settings for UniPhier Family */
   8
   9 #ifndef __CONFIG_UNIPHIER_COMMON_H__
  10 #define __CONFIG_UNIPHIER_COMMON_H__
  11
  12 #define CONFIG_I2C_EEPROM
  13 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  10
  14
  15 #ifdef CONFIG_SYS_NS16550_SERIAL
  16 #define CONFIG_SYS_NS16550_COM1         CONFIG_SUPPORT_CARD_UART_BASE
  17 #define CONFIG_SYS_NS16550_CLK          12288000
  18 #define CONFIG_SYS_NS16550_REG_SIZE     -2
  19 #endif
  20
  21 #define CONFIG_SMC911X
  22
  23 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */
  24 #define CONFIG_SMC911X_BASE     0
  25 #define CONFIG_SMC911X_32_BIT
  26
  27 /*-----------------------------------------------------------------------
  28  * MMU and Cache Setting
  29  *----------------------------------------------------------------------*/
  30
  31 /* Comment out the following to enable L1 cache */
  32 /* #define CONFIG_SYS_ICACHE_OFF */
  33 /* #define CONFIG_SYS_DCACHE_OFF */
  34
  35 #define CONFIG_SYS_CACHELINE_SIZE       32
  36
  37 /* Comment out the following to disable L2 cache */
  38 #define CONFIG_UNIPHIER_L2CACHE_ON
  39
  40 #define CONFIG_DISPLAY_CPUINFO
  41 #define CONFIG_DISPLAY_BOARDINFO
  42 #define CONFIG_MISC_INIT_F
  43 #define CONFIG_BOARD_EARLY_INIT_F
  44 #define CONFIG_BOARD_EARLY_INIT_R
  45 #define CONFIG_BOARD_LATE_INIT
  46
  47 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
  48
  49 #define CONFIG_TIMESTAMP
  50
  51 /* FLASH related */
  52 #define CONFIG_MTD_DEVICE
  53
  54 /*
  55  * uncomment the following to disable FLASH related code.
  56  */
  57 /* #define CONFIG_SYS_NO_FLASH */
  58
  59 #define CONFIG_FLASH_CFI_DRIVER
  60 #define CONFIG_SYS_FLASH_CFI
  61
  62 #define CONFIG_SYS_MAX_FLASH_SECT       256
  63 #define CONFIG_SYS_MONITOR_BASE         0
  64 #define CONFIG_SYS_FLASH_BASE           0
  65
  66 /*
  67  * flash_toggle does not work for out supoort card.
  68  * We need to use flash_status_poll.
  69  */
  70 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
  71
  72 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  73
  74 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
  75
  76 /* serial console configuration */
  77 #define CONFIG_BAUDRATE                 115200
  78
  79
  80 #if !defined(CONFIG_SPL_BUILD)
  81 #define CONFIG_USE_ARCH_MEMSET
  82 #define CONFIG_USE_ARCH_MEMCPY
  83 #endif
  84
  85 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
  86
  87 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
  88 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
  89 /* Print Buffer Size */
  90 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  91 #define CONFIG_SYS_MAXARGS              16      /* max number of command */
  92 /* Boot Argument Buffer Size */
  93 #define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
  94
  95 #define CONFIG_CONS_INDEX               1
  96
  97 /* #define CONFIG_ENV_IS_NOWHERE */
  98 /* #define CONFIG_ENV_IS_IN_NAND */
  99 #define CONFIG_ENV_IS_IN_MMC
 100 #define CONFIG_ENV_OFFSET                       0x80000
 101 #define CONFIG_ENV_SIZE                         0x2000
 102 /* #define CONFIG_ENV_OFFSET_REDUND     (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
 103
 104 #define CONFIG_SYS_MMC_ENV_DEV          0
 105 #define CONFIG_SYS_MMC_ENV_PART         1
 106
 107 /* Time clock 1MHz */
 108 #define CONFIG_SYS_TIMER_RATE                   1000000
 109
 110 /*
 111  * By default, ARP timeout is 5 sec.
 112  * The first ARP request does not seem to work.
 113  * So we need to retry ARP request anyway.
 114  * We want to shrink the interval until the second ARP request.
 115  */
 116 #define CONFIG_ARP_TIMEOUT      500UL  /* 0.5 msec */
 117
 118 #define CONFIG_SYS_MAX_NAND_DEVICE                      1
 119 #define CONFIG_SYS_NAND_MAX_CHIPS                       2
 120 #define CONFIG_SYS_NAND_ONFI_DETECTION
 121
 122 #define CONFIG_NAND_DENALI_ECC_SIZE                     1024
 123
 124 #ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
 125 #define CONFIG_SYS_NAND_REGS_BASE                       0xf8100000
 126 #define CONFIG_SYS_NAND_DATA_BASE                       0xf8000000
 127 #else
 128 #define CONFIG_SYS_NAND_REGS_BASE                       0x68100000
 129 #define CONFIG_SYS_NAND_DATA_BASE                       0x68000000
 130 #endif
 131
 132 #define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_DATA_BASE + 0x10)
 133
 134 #define CONFIG_SYS_NAND_USE_FLASH_BBT
 135 #define CONFIG_SYS_NAND_BAD_BLOCK_POS                   0
 136
 137 /* USB */
 138 #define CONFIG_USB_MAX_CONTROLLER_COUNT         2
 139 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      4
 140 #define CONFIG_CMD_FAT
 141 #define CONFIG_FAT_WRITE
 142 #define CONFIG_DOS_PARTITION
 143
 144 /* SD/MMC */
 145 #define CONFIG_CMD_MMC
 146 #define CONFIG_SUPPORT_EMMC_BOOT
 147 #define CONFIG_GENERIC_MMC
 148
 149 /* memtest works on */
 150 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 151 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + 0x01000000)
 152
 153 #define CONFIG_BOOTDELAY                        3
 154 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 155
 156 /*
 157  * Network Configuration
 158  */
 159 #define CONFIG_SERVERIP                 192.168.11.1
 160 #define CONFIG_IPADDR                   192.168.11.10
 161 #define CONFIG_GATEWAYIP                192.168.11.1
 162 #define CONFIG_NETMASK                  255.255.255.0
 163
 164 #define CONFIG_LOADADDR                 0x84000000
 165 #define CONFIG_SYS_LOAD_ADDR            CONFIG_LOADADDR
 166
 167 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
 168
 169 #define CONFIG_BOOTCOMMAND              "run $bootmode"
 170
 171 #define CONFIG_ROOTPATH                 "/nfs/root/path"
 172 #define CONFIG_NFSBOOTCOMMAND                                           \
 173         "setenv bootargs $bootargs root=/dev/nfs rw "                   \
 174         "nfsroot=$serverip:$rootpath "                                  \
 175         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
 176                 "run __nfsboot"
 177
 178 #ifdef CONFIG_FIT
 179 #define CONFIG_BOOTFILE                 "fitImage"
 180 #define LINUXBOOT_ENV_SETTINGS \
 181         "fit_addr=0x00100000\0" \
 182         "fit_addr_r=0x84100000\0" \
 183         "fit_size=0x00f00000\0" \
 184         "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
 185                 "bootm $fit_addr\0" \
 186         "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
 187                 "bootm $fit_addr_r\0" \
 188         "tftpboot=tftpboot $fit_addr_r $bootfile &&" \
 189                 "bootm $fit_addr_r\0" \
 190         "__nfsboot=run tftpboot\0"
 191 #else
 192 #define CONFIG_CMD_BOOTZ
 193 #define CONFIG_BOOTFILE                 "zImage"
 194 #define LINUXBOOT_ENV_SETTINGS \
 195         "fdt_addr=0x00100000\0" \
 196         "fdt_addr_r=0x84100000\0" \
 197         "fdt_size=0x00008000\0" \
 198         "kernel_addr=0x00200000\0" \
 199         "kernel_addr_r=0x80208000\0" \
 200         "kernel_size=0x00800000\0" \
 201         "ramdisk_addr=0x00a00000\0" \
 202         "ramdisk_addr_r=0x84a00000\0" \
 203         "ramdisk_size=0x00600000\0" \
 204         "ramdisk_file=rootfs.cpio.uboot\0" \
 205         "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \
 206                 "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
 207         "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \
 208                 "cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \
 209                 "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \
 210                 "setexpr fdt_addr_r $nor_base + $fdt_addr &&" \
 211                 "run boot_common\0" \
 212         "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \
 213                 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
 214                 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
 215                 "run boot_common\0" \
 216         "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \
 217                 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
 218                 "tftpboot $fdt_addr_r $fdt_file &&" \
 219                 "run boot_common\0" \
 220         "__nfsboot=tftpboot $kernel_addr_r $bootfile &&" \
 221                 "tftpboot $fdt_addr_r $fdt_file &&" \
 222                 "tftpboot $fdt_addr_r $fdt_file &&" \
 223                 "setenv ramdisk_addr_r - &&" \
 224                 "run boot_common\0"
 225 #endif
 226
 227 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 228         "netdev=eth0\0"                                         \
 229         "verify=n\0"                                            \
 230         "nor_base=0x42000000\0"                                 \
 231         "emmcupdate=mmcsetn &&"                                 \
 232                 "mmc partconf $mmc_first_dev 0 1 1 &&"          \
 233                 "mmc erase 0 800 &&"                            \
 234                 "tftpboot u-boot-spl.bin &&"                    \
 235                 "mmc write $loadaddr 0 80 &&"                   \
 236                 "tftpboot u-boot.img &&"                        \
 237                 "mmc write $loadaddr 80 780\0"                  \
 238         "nandupdate=nand erase 0 0x00100000 &&"                 \
 239                 "tftpboot u-boot-spl.bin &&"                    \
 240                 "nand write $loadaddr 0 0x00010000 &&"          \
 241                 "tftpboot u-boot.img &&"                        \
 242                 "nand write $loadaddr 0x00010000 0x000f0000\0"  \
 243         LINUXBOOT_ENV_SETTINGS
 244
 245 #define CONFIG_SYS_BOOTMAPSZ                    0x20000000
 246
 247 #define CONFIG_SYS_SDRAM_BASE           0x80000000
 248 #define CONFIG_NR_DRAM_BANKS            2
 249
 250 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \
 251         defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
 252         defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
 253 #define CONFIG_SPL_TEXT_BASE            0x00040000
 254 #else
 255 #define CONFIG_SPL_TEXT_BASE            0x00100000
 256 #endif
 257
 258 #define CONFIG_SPL_STACK                (0x00100000)
 259 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_TEXT_BASE)
 260
 261 #define CONFIG_PANIC_HANG
 262
 263 #define CONFIG_SPL_FRAMEWORK
 264 #define CONFIG_SPL_SERIAL_SUPPORT
 265 #define CONFIG_SPL_NAND_SUPPORT
 266 #define CONFIG_SPL_MMC_SUPPORT
 267
 268 #define CONFIG_SPL_LIBCOMMON_SUPPORT    /* for mem_malloc_init */
 269 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 270
 271 #define CONFIG_SPL_BOARD_INIT
 272
 273 #define CONFIG_SYS_NAND_U_BOOT_OFFS             0x10000
 274 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x80
 275
 276 #define CONFIG_SPL_MAX_FOOTPRINT                0x10000
 277
 278 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */