2 * Copyright (C) 2012-2015 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 /* U-Boot - Common settings for UniPhier Family */
11 #ifndef __CONFIG_UNIPHIER_COMMON_H__
12 #define __CONFIG_UNIPHIER_COMMON_H__
14 #define CONFIG_ARMV7_PSCI_1_0
16 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
19 #define CONFIG_CMD_UNZIP
22 /*-----------------------------------------------------------------------
23 * MMU and Cache Setting
24 *----------------------------------------------------------------------*/
26 /* Comment out the following to enable L1 cache */
27 /* #define CONFIG_SYS_ICACHE_OFF */
28 /* #define CONFIG_SYS_DCACHE_OFF */
30 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
32 #define CONFIG_TIMESTAMP
35 #define CONFIG_MTD_DEVICE
37 #define CONFIG_SMC911X_32_BIT
38 /* dummy: referenced by examples/standalone/smc911x_eeprom.c */
39 #define CONFIG_SMC911X_BASE 0
41 #ifdef CONFIG_MICRO_SUPPORT_CARD
42 #define CONFIG_SMC911X
44 #define CONFIG_SYS_NO_FLASH
47 #define CONFIG_FLASH_CFI_DRIVER
48 #define CONFIG_SYS_FLASH_CFI
50 #define CONFIG_SYS_MAX_FLASH_SECT 256
51 #define CONFIG_SYS_MONITOR_BASE 0
52 #define CONFIG_SYS_MONITOR_LEN 0x00080000 /* 512KB */
53 #define CONFIG_SYS_FLASH_BASE 0
56 * flash_toggle does not work for our support card.
57 * We need to use flash_status_poll.
59 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL
61 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
63 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
65 /* serial console configuration */
66 #define CONFIG_BAUDRATE 115200
68 #define CONFIG_SYS_LONGHELP /* undef to save memory */
70 #define CONFIG_CMDLINE_EDITING /* add command line history */
71 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
72 /* Print Buffer Size */
73 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
74 #define CONFIG_SYS_MAXARGS 16 /* max number of command */
75 /* Boot Argument Buffer Size */
76 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
78 #define CONFIG_CONS_INDEX 1
80 /* #define CONFIG_ENV_IS_NOWHERE */
81 /* #define CONFIG_ENV_IS_IN_NAND */
82 #define CONFIG_ENV_IS_IN_MMC
83 #define CONFIG_ENV_OFFSET 0x100000
84 #define CONFIG_ENV_SIZE 0x2000
85 /* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
87 #define CONFIG_SYS_MMC_ENV_DEV 0
88 #define CONFIG_SYS_MMC_ENV_PART 1
90 #ifdef CONFIG_ARMV8_MULTIENTRY
91 #define CPU_RELEASE_ADDR 0x80000000
92 #define COUNTER_FREQUENCY 50000000
94 #define GICD_BASE 0x5fe00000
95 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
96 #define GICR_BASE 0x5fe40000
97 #elif defined(CONFIG_ARCH_UNIPHIER_LD20)
98 #define GICR_BASE 0x5fe80000
100 #elif !defined(CONFIG_ARM64)
101 /* Time clock 1MHz */
102 #define CONFIG_SYS_TIMER_RATE 1000000
105 #define CONFIG_SYS_MAX_NAND_DEVICE 1
106 #define CONFIG_SYS_NAND_MAX_CHIPS 2
107 #define CONFIG_SYS_NAND_ONFI_DETECTION
109 #define CONFIG_NAND_DENALI_ECC_SIZE 1024
111 #ifdef CONFIG_ARCH_UNIPHIER_SLD3
112 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000
113 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000
115 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000
116 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
119 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10)
121 #define CONFIG_SYS_NAND_USE_FLASH_BBT
122 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
125 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 4
126 #define CONFIG_FAT_WRITE
129 #define CONFIG_SUPPORT_EMMC_BOOT
130 #define CONFIG_GENERIC_MMC
132 /* memtest works on */
133 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
134 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
137 * Network Configuration
139 #define CONFIG_SERVERIP 192.168.11.1
140 #define CONFIG_IPADDR 192.168.11.10
141 #define CONFIG_GATEWAYIP 192.168.11.1
142 #define CONFIG_NETMASK 255.255.255.0
144 #define CONFIG_LOADADDR 0x84000000
145 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
147 #define CONFIG_CMDLINE_EDITING /* add command line history */
149 #if defined(CONFIG_ARM64) && !defined(CONFIG_ARMV8_MULTIENTRY)
150 /* ARM Trusted Firmware */
151 #define BOOT_IMAGES \
152 "second_image=bl1.bin\0" \
153 "third_image=fip.bin\0"
155 #define BOOT_IMAGES \
156 "second_image=u-boot-spl.bin\0" \
157 "third_image=u-boot.bin\0"
160 #define CONFIG_BOOTCOMMAND "run $bootmode"
162 #define CONFIG_ROOTPATH "/nfs/root/path"
163 #define CONFIG_NFSBOOTCOMMAND \
164 "setenv bootargs $bootargs root=/dev/nfs rw " \
165 "nfsroot=$serverip:$rootpath " \
166 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \
170 #define CONFIG_BOOTFILE "fitImage"
171 #define LINUXBOOT_ENV_SETTINGS \
172 "fit_addr=0x00100000\0" \
173 "fit_addr_r=0x84100000\0" \
174 "fit_size=0x00f00000\0" \
175 "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
176 "bootm $fit_addr\0" \
177 "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \
178 "bootm $fit_addr_r\0" \
179 "tftpboot=tftpboot $fit_addr_r $bootfile &&" \
180 "bootm $fit_addr_r\0" \
181 "__nfsboot=run tftpboot\0"
184 #define CONFIG_BOOTFILE "Image.gz"
185 #define LINUXBOOT_CMD "booti"
186 #define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0"
187 #define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0"
189 #define CONFIG_BOOTFILE "zImage"
190 #define LINUXBOOT_CMD "bootz"
191 #define KERNEL_ADDR_LOAD "kernel_addr_load=0x80208000\0"
192 #define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0"
194 #define LINUXBOOT_ENV_SETTINGS \
195 "fdt_addr=0x00100000\0" \
196 "fdt_addr_r=0x84100000\0" \
197 "fdt_size=0x00008000\0" \
198 "kernel_addr=0x00200000\0" \
201 "kernel_size=0x00800000\0" \
202 "ramdisk_addr=0x00a00000\0" \
203 "ramdisk_addr_r=0x84a00000\0" \
204 "ramdisk_size=0x00600000\0" \
205 "ramdisk_file=rootfs.cpio.uboot\0" \
206 "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
207 "if test $kernel_addr_load = $kernel_addr_r; then " \
210 "unzip $kernel_addr_load $kernel_addr_r; " \
212 LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \
213 "norboot=setexpr kernel_addr_nor $nor_base + $kernel_addr && " \
214 "setexpr kernel_size_div4 $kernel_size / 4 && " \
215 "cp $kernel_addr_nor $kernel_addr_load $kernel_size_div4 && " \
216 "setexpr ramdisk_addr_nor $nor_base + $ramdisk_addr && " \
217 "setexpr ramdisk_size_div4 $ramdisk_size / 4 && " \
218 "cp $ramdisk_addr_nor $ramdisk_addr_r $ramdisk_size_div4 && " \
219 "setexpr fdt_addr_nor $nor_base + $fdt_addr && " \
220 "setexpr fdt_size_div4 $fdt_size / 4 && " \
221 "cp $fdt_addr_nor $fdt_addr_r $fdt_size_div4 && " \
222 "run boot_common\0" \
223 "nandboot=nand read $kernel_addr_load $kernel_addr $kernel_size && " \
224 "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \
225 "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \
226 "run boot_common\0" \
227 "tftpboot=tftpboot $kernel_addr_load $bootfile && " \
228 "tftpboot $ramdisk_addr_r $ramdisk_file &&" \
229 "tftpboot $fdt_addr_r $fdt_file &&" \
230 "run boot_common\0" \
231 "__nfsboot=tftpboot $kernel_addr_load $bootfile && " \
232 "tftpboot $fdt_addr_r $fdt_file &&" \
233 "setenv ramdisk_addr_r - &&" \
237 #define CONFIG_EXTRA_ENV_SETTINGS \
240 "initrd_high=0xffffffffffffffff\0" \
241 "nor_base=0x42000000\0" \
242 "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \
243 "tftpboot $tmp_addr $second_image && " \
244 "setexpr tmp_addr $nor_base + 0x70000 && " \
245 "tftpboot $tmp_addr $third_image\0" \
246 "emmcupdate=mmcsetn &&" \
247 "mmc partconf $mmc_first_dev 0 1 1 &&" \
248 "tftpboot $second_image && " \
249 "mmc write $loadaddr 0 100 && " \
250 "tftpboot $third_image && " \
251 "mmc write $loadaddr 100 700\0" \
252 "nandupdate=nand erase 0 0x00100000 &&" \
253 "tftpboot $second_image && " \
254 "nand write $loadaddr 0 0x00020000 && " \
255 "tftpboot $third_image && " \
256 "nand write $loadaddr 0x00020000 0x000e0000\0" \
258 LINUXBOOT_ENV_SETTINGS
260 #define CONFIG_SYS_BOOTMAPSZ 0x20000000
262 #define CONFIG_SYS_SDRAM_BASE 0x80000000
263 #define CONFIG_NR_DRAM_BANKS 3
264 /* for LD20; the last 64 byte is used for dynamic DDR PHY training */
265 #define CONFIG_SYS_MEM_TOP_HIDE 64
267 #define CONFIG_PANIC_HANG
269 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
272 #if defined(CONFIG_ARM64)
273 #define CONFIG_SPL_TEXT_BASE 0x30000000
274 #elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
275 defined(CONFIG_ARCH_UNIPHIER_LD4) || \
276 defined(CONFIG_ARCH_UNIPHIER_SLD8)
277 #define CONFIG_SPL_TEXT_BASE 0x00040000
279 #define CONFIG_SPL_TEXT_BASE 0x00100000
282 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
283 #define CONFIG_SPL_STACK (0x30014c00)
284 #elif defined(CONFIG_ARCH_UNIPHIER_LD20)
285 #define CONFIG_SPL_STACK (0x3001c000)
287 #define CONFIG_SPL_STACK (0x00100000)
290 #define CONFIG_SPL_FRAMEWORK
292 #define CONFIG_SPL_BOARD_LOAD_IMAGE
295 #define CONFIG_SPL_BOARD_INIT
297 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
299 /* subtract sizeof(struct image_header) */
300 #define CONFIG_SYS_UBOOT_BASE (0x70000 - 0x40)
302 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
303 #define CONFIG_SPL_MAX_FOOTPRINT 0x10000
304 #if defined(CONFIG_ARCH_UNIPHIER_LD20)
305 #define CONFIG_SPL_MAX_SIZE 0x14000
307 #define CONFIG_SPL_MAX_SIZE 0x10000
309 #if defined(CONFIG_ARCH_UNIPHIER_LD11)
310 #define CONFIG_SPL_BSS_START_ADDR 0x30012000
311 #elif defined(CONFIG_ARCH_UNIPHIER_LD20)
312 #define CONFIG_SPL_BSS_START_ADDR 0x30016000
314 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000
316 #define CONFIG_SPL_PAD_TO 0x20000
318 #endif /* __CONFIG_UNIPHIER_COMMON_H__ */