2 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
5 * SPDX-License-Identifier: GPL-2.0+
12 * High Level Configuration Options
15 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
16 #define CONFIG_V38B 1 /* ...on V38B board */
18 #define CONFIG_SYS_TEXT_BASE 0xFF000000
20 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
22 #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
23 #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
25 #undef CONFIG_HW_WATCHDOG /* don't use watchdog */
27 #define CONFIG_NETCONSOLE 1
29 #define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
30 #define CONFIG_MISC_INIT_R
32 #define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */
34 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
37 * Serial console configuration
39 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
40 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
45 #define SDRAM_DDR 1 /* is DDR */
46 /* Settings for XLB = 132 MHz */
47 #define SDRAM_MODE 0x018D0000
48 #define SDRAM_EMODE 0x40090000
49 #define SDRAM_CONTROL 0x704f0f00
50 #define SDRAM_CONFIG1 0x73722930
51 #define SDRAM_CONFIG2 0x47770000
52 #define SDRAM_TAPDELAY 0x10000000
61 #define CONFIG_USB_OHCI
62 #define CONFIG_USB_CLOCK 0x0001BBBB
63 #define CONFIG_USB_CONFIG 0x00001000
68 #define CONFIG_BOOTP_BOOTFILESIZE
69 #define CONFIG_BOOTP_BOOTPATH
70 #define CONFIG_BOOTP_GATEWAY
71 #define CONFIG_BOOTP_HOSTNAME
74 * Command line configuration.
76 #define CONFIG_CMD_IDE
77 #define CONFIG_CMD_IRQ
78 #define CONFIG_CMD_JFFS2
79 #define CONFIG_CMD_SDRAM
81 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
84 * Boot low with 16 MB Flash
86 #define CONFIG_SYS_LOWBOOT 1
87 #define CONFIG_SYS_LOWBOOT16 1
93 #define CONFIG_PREBOOT "echo;" \
94 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
97 #undef CONFIG_BOOTARGS
99 #define CONFIG_EXTRA_ENV_SETTINGS \
100 "bootcmd=run net_nfs\0" \
102 "baudrate=115200\0" \
103 "preboot=echo;echo Type \"run flash_nfs\" to mount root " \
104 "filesystem over NFS; echo\0" \
106 "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
107 "addip=setenv bootargs $(bootargs) " \
108 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
109 "$(netmask):$(hostname):$(netdev):off panic=1\0" \
110 "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
111 "flash_self=run ramargs addip;bootm $(kernel_addr) " \
112 "$(ramdisk_addr)\0" \
113 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
114 "nfsargs=setenv bootargs root=/dev/nfs rw " \
115 "nfsroot=$(serverip):$(rootpath) wdt=off\0" \
118 "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
119 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
120 "cp.b 200000 ff000000 $(filesize);" \
121 "prot on ff000000 ff03ffff\0" \
122 "load=tftp 200000 $(u-boot)\0" \
123 "netmask=255.255.0.0\0" \
124 "ipaddr=192.168.160.18\0" \
125 "serverip=192.168.1.1\0" \
126 "bootfile=/tftpboot/v38b/uImage\0" \
127 "u-boot=/tftpboot/v38b/u-boot.bin\0" \
130 #define CONFIG_BOOTCOMMAND "run net_nfs"
133 * IPB Bus clocking configuration.
135 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
138 * Flash configuration - use CFI driver
140 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
141 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
142 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
143 #define CONFIG_SYS_FLASH_BASE 0xFF000000
144 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
145 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
146 #define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */
147 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
151 * Environment settings
153 #define CONFIG_ENV_IS_IN_FLASH 1
154 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
155 #define CONFIG_ENV_SIZE 0x10000
156 #define CONFIG_ENV_SECT_SIZE 0x10000
157 #define CONFIG_ENV_OVERWRITE 1
162 #define CONFIG_SYS_MBAR 0xF0000000
163 #define CONFIG_SYS_SDRAM_BASE 0x00000000
164 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
166 /* Use SRAM until RAM will be available */
167 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
168 #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
173 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
174 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
175 # define CONFIG_SYS_RAMBOOT 1
178 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
179 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
180 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
183 * Ethernet configuration
185 #define CONFIG_MPC5xxx_FEC 1
186 #define CONFIG_MPC5xxx_FEC_MII100
187 #define CONFIG_PHY_ADDR 0x00
193 #define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404
196 * Miscellaneous configurable options
198 #define CONFIG_SYS_LONGHELP /* undef to save memory */
199 #if defined(CONFIG_CMD_KGDB)
200 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
202 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
204 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
205 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
206 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
208 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
209 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
211 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
213 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
214 #if defined(CONFIG_CMD_KGDB)
215 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
219 * Various low-level settings
221 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
222 #define CONFIG_SYS_HID0_FINAL HID0_ICE
224 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
225 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
226 #define CONFIG_SYS_BOOTCS_CFG 0x00047801
227 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
228 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
230 #define CONFIG_SYS_CS_BURST 0x00000000
231 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
233 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
236 * IDE/ATA (supports IDE harddisk)
238 #undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
239 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
240 #undef CONFIG_IDE_LED /* LED for ide not supported */
242 #define CONFIG_IDE_RESET /* reset for ide supported */
243 #define CONFIG_IDE_PREINIT
245 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
246 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
248 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
250 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
252 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
254 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */
256 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
258 #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
264 #define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
266 typedef unsigned int led_id_t;
268 #define __led_toggle(_msk) \
270 *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \
273 #define __led_set(_msk, _st) \
276 *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \
278 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \
281 #define __led_init(_msk, st) \
283 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \
285 #endif /* __ASSEMBLY__ */
287 #endif /* __CONFIG_H */