2 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
4 * SPDX-License-Identifier: GPL-2.0+
8 * This file contains the configuration parameters for the VCT board
14 * vct_premium_onenand_small
17 * vct_platinum_onenand
18 * vct_platinum_onenand_small
20 * vct_platinumavc_small
21 * vct_platinumavc_onenand
22 * vct_platinumavc_onenand_small
28 #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
29 #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
31 #define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
33 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
34 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
35 #define CONFIG_SYS_MALLOC_LEN (1 << 20)
36 #define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
37 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000
39 #if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
40 #define CONFIG_VCT_NOR
46 #ifdef CONFIG_VCT_PLATINUMAVC
47 #define UART_1_BASE 0xBDC30000
49 #define UART_1_BASE 0xBF89C000
52 #define CONFIG_SYS_NS16550_SERIAL
53 #define CONFIG_SYS_NS16550_REG_SIZE -4
54 #define CONFIG_SYS_NS16550_COM1 UART_1_BASE
55 #define CONFIG_CONS_INDEX 1
56 #define CONFIG_SYS_NS16550_CLK 921600
61 #define CONFIG_SYS_SDRAM_BASE 0x80000000
62 #define CONFIG_SYS_MBYTES_SDRAM 128
63 #define CONFIG_SYS_MEMTEST_START 0x80200000
64 #define CONFIG_SYS_MEMTEST_END 0x80400000
65 #define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
67 #if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
69 * SMSC91C11x Network Card
71 #define CONFIG_SMC911X
72 #define CONFIG_SMC911X_BASE 0x00000000
73 #define CONFIG_SMC911X_32_BIT
74 #define CONFIG_NET_RETRY_COUNT 20
82 * Only Premium/Platinum have ethernet support right now
84 #if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
85 !defined(CONFIG_VCT_SMALL_IMAGE)
89 * Only Premium/Platinum have USB-EHCI support right now
91 #if (defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)) && \
92 !defined(CONFIG_VCT_SMALL_IMAGE)
95 #if defined(CONFIG_CMD_USB)
96 #define CONFIG_SUPPORT_VFAT
101 #define CONFIG_USB_EHCI_VCT /* on VCT platform */
102 #define CONFIG_EHCI_MMIO_BIG_ENDIAN
103 #define CONFIG_EHCI_DESC_BIG_ENDIAN
104 #define CONFIG_EHCI_IS_TDI
105 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
106 #endif /* CONFIG_CMD_USB */
111 #define CONFIG_BOOTP_BOOTFILESIZE
112 #define CONFIG_BOOTP_BOOTPATH
113 #define CONFIG_BOOTP_GATEWAY
114 #define CONFIG_BOOTP_HOSTNAME
115 #define CONFIG_BOOTP_SUBNETMASK
118 * Miscellaneous configurable options
120 #define CONFIG_SYS_LONGHELP /* undef to save memory */
121 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
122 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
123 #define CONFIG_CMDLINE_EDITING /* add command line history */
126 * FLASH and environment organization
128 #if defined(CONFIG_VCT_NOR)
129 #define CONFIG_FLASH_NOT_MEM_MAPPED
132 * We need special accessor functions for the CFI FLASH driver. This
133 * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
135 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
138 * For the non-memory-mapped NOR FLASH, we need to define the
139 * NOR FLASH area. This can't be detected via the addr2info()
140 * function, since we check for flash access in the very early
141 * U-Boot code, before the NOR FLASH is detected.
143 #define CONFIG_FLASH_BASE 0xb0000000
144 #define CONFIG_FLASH_END 0xbfffffff
147 * CFI driver settings
149 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
150 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
151 #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
152 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
154 #define CONFIG_SYS_FLASH_BASE 0xb0000000
155 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
156 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
157 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
159 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
160 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
162 #ifdef CONFIG_ENV_IS_IN_FLASH
163 #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
164 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
165 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
167 /* Address and size of Redundant Environment Sector */
168 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
169 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
170 #endif /* CONFIG_ENV_IS_IN_FLASH */
171 #endif /* CONFIG_VCT_NOR */
173 #if defined(CONFIG_VCT_ONENAND)
174 #define CONFIG_USE_ONENAND_BOARD_INIT
175 #define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
176 #define CONFIG_SYS_FLASH_BASE 0x00000000
177 #define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
178 #define CONFIG_ENV_SIZE (128 << 10) /* erase size */
179 #endif /* CONFIG_VCT_ONENAND */
184 #define CONFIG_SYS_I2C
185 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
186 #define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */
187 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f
190 * Software (bit-bang) I2C driver configuration
192 #define CONFIG_SYS_GPIO_I2C_SCL 11
193 #define CONFIG_SYS_GPIO_I2C_SDA 10
196 int vct_gpio_dir(int pin, int dir);
197 void vct_gpio_set(int pin, int val);
198 int vct_gpio_get(int pin);
201 #define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
202 #define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
203 #define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
204 #define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
205 #define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
206 #define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
207 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
209 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
211 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
212 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
213 /* 32 byte page write mode using*/
214 /* last 5 bits of the address */
215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
217 #define CONFIG_BOOTCOMMAND "run test3"
222 #if defined(CONFIG_VCT_ONENAND)
223 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
224 #define CONFIG_MTD_PARTITIONS
226 #define MTDIDS_DEFAULT "onenand0=onenand"
227 #define MTDPARTS_DEFAULT "mtdparts=onenand:128k(u-boot)," \
234 * We need a small, stripped down image to fit into the first 128k OneNAND
235 * erase block (gzipped). This image only needs basic commands for FLASH
236 * (NOR/OneNAND) usage and Linux kernel booting.
238 #if defined(CONFIG_VCT_SMALL_IMAGE)
239 #undef CONFIG_SMC911X
240 #undef CONFIG_SYS_I2C_SOFT
242 #undef CONFIG_SYS_LONGHELP
243 #undef CONFIG_TIMESTAMP
244 #endif /* CONFIG_VCT_SMALL_IMAGE */
246 #endif /* __CONFIG_H */