2 * (C) Copyright 2000-2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * board/config.h - configuration options, board specific
32 * High Level Configuration Options
36 #define CONFIG_405GP 1 /* This is a PPC405 CPU */
37 #define CONFIG_4xx 1 /* ...member of PPC4xx family */
38 #define CONFIG_WALNUT 1 /* ...on a WALNUT board */
39 /* ...and on a SYCAMORE board */
41 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
43 #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
45 #define CONFIG_PREBOOT "echo;" \
46 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
49 #undef CONFIG_BOOTARGS
51 #define CONFIG_EXTRA_ENV_SETTINGS \
54 "nfsargs=setenv bootargs root=/dev/nfs rw " \
55 "nfsroot=${serverip}:${rootpath}\0" \
56 "ramargs=setenv bootargs root=/dev/ram rw\0" \
57 "addip=setenv bootargs ${bootargs} " \
58 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
59 ":${hostname}:${netdev}:off panic=1\0" \
60 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
61 "flash_nfs=run nfsargs addip addtty;" \
62 "bootm ${kernel_addr}\0" \
63 "flash_self=run ramargs addip addtty;" \
64 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
65 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
67 "rootpath=/opt/eldk/ppc_4xx\0" \
68 "bootfile=/tftpboot/walnut/uImage\0" \
69 "kernel_addr=fff80000\0" \
70 "ramdisk_addr=fff80000\0" \
71 "initrd_high=30000000\0" \
72 "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \
73 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
74 "cp.b 100000 fffc0000 40000;" \
75 "setenv filesize;saveenv\0" \
76 "upd=run load;run update\0" \
78 #define CONFIG_BOOTCOMMAND "run net_nfs"
81 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
83 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
86 #define CONFIG_BAUDRATE 115200
88 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
89 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
91 #define CONFIG_MII 1 /* MII PHY management */
92 #define CONFIG_PHY_ADDR 1 /* PHY address */
94 #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
96 #define CONFIG_NETCONSOLE /* include NetConsole support */
97 #define CONFIG_NET_MULTI /* needed for NetConsole */
99 #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */
101 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
119 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
120 #include <cmd_confdefs.h>
122 #undef CONFIG_WATCHDOG /* watchdog disabled */
124 #define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
127 * Miscellaneous configurable options
129 #define CFG_LONGHELP /* undef to save memory */
130 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
131 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
132 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
134 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
136 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
137 #define CFG_MAXARGS 16 /* max number of command args */
138 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
140 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
141 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
144 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
145 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
146 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
147 * The Linux BASE_BAUD define should match this configuration.
148 * baseBaud = cpuClock/(uartDivisor*16)
149 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
150 * set Linux BASE_BAUD to 403200.
152 #undef CONFIG_SERIAL_SOFTWARE_FIFO
153 #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
154 #undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
155 #define CFG_BASE_BAUD 691200
157 /* The following table includes the supported baudrates */
158 #define CFG_BAUDRATE_TABLE \
159 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
161 #define CFG_LOAD_ADDR 0x100000 /* default load address */
162 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
164 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
166 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
167 #define CONFIG_LOOPW 1 /* enable loopw command */
168 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
169 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
170 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
172 /*-----------------------------------------------------------------------
174 *-----------------------------------------------------------------------
176 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
177 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
178 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
179 #define CFG_I2C_SLAVE 0x7F
181 #define CFG_I2C_MULTI_EEPROMS
182 #define CFG_I2C_EEPROM_ADDR (0xa8>>1)
183 #define CFG_I2C_EEPROM_ADDR_LEN 1
184 #define CFG_EEPROM_PAGE_WRITE_ENABLE
185 #define CFG_EEPROM_PAGE_WRITE_BITS 3
186 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
188 /*-----------------------------------------------------------------------
190 *-----------------------------------------------------------------------
192 #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
193 #define PCI_HOST_FORCE 1 /* configure as pci host */
194 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
196 #define CONFIG_PCI /* include pci support */
197 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
198 #define CONFIG_PCI_PNP /* do pci plug-and-play */
199 /* resource configuration */
200 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
202 #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
203 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
204 #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
205 #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
206 #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
207 #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
208 #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
209 #define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
211 /*-----------------------------------------------------------------------
212 * Start addresses for the final memory configuration
213 * (Set up by the startup code)
214 * Please note that CFG_SDRAM_BASE _must_ start at 0
216 #define CFG_SDRAM_BASE 0x00000000
217 #define CFG_FLASH_BASE 0xFFF80000
218 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
219 #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
220 #define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
223 * Define here the location of the environment variables (FLASH or NVRAM).
224 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
225 * supported for backward compatibility.
228 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
230 #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
234 * For booting Linux, the board info and command line data
235 * have to be in the first 8 MB of memory, since this is
236 * the maximum mapped by the Linux kernel during initialization.
238 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
240 /*-----------------------------------------------------------------------
243 #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
244 #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
246 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
247 #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
249 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
250 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
252 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
254 #define CFG_FLASH_ADDR0 0x5555
255 #define CFG_FLASH_ADDR1 0x2aaa
256 #define CFG_FLASH_WORD_SIZE unsigned char
258 #ifdef CFG_ENV_IS_IN_FLASH
259 #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
260 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
261 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
263 /* Address and size of Redundant Environment Sector */
264 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
265 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
266 #endif /* CFG_ENV_IS_IN_FLASH */
268 /*-----------------------------------------------------------------------
271 #define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
272 #define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */
274 #ifdef CFG_ENV_IS_IN_NVRAM
275 #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
276 #define CFG_ENV_ADDR \
277 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
280 /*-----------------------------------------------------------------------
281 * Cache Configuration
283 #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
284 /* have only 8kB, 16kB is save here */
285 #define CFG_CACHELINE_SIZE 32 /* ... */
286 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
287 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
290 /*-----------------------------------------------------------------------
291 * External Bus Controller (EBC) Setup
294 /* Memory Bank 0 (Flash Bank 0) initialization */
295 #define CFG_EBC_PB0AP 0x9B015480
296 #define CFG_EBC_PB0CR 0xFFF18000 /* BAS=0xFFF,BS=1MB,BU=R/W,BW=8bit */
298 #define CFG_EBC_PB1AP 0x02815480
299 #define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
301 #define CFG_EBC_PB2AP 0x04815A80
302 #define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
304 #define CFG_EBC_PB3AP 0x01815280
305 #define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
307 #define CFG_EBC_PB7AP 0x01815280
308 #define CFG_EBC_PB7CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
310 /*-----------------------------------------------------------------------
311 * External peripheral base address
312 *-----------------------------------------------------------------------
314 #define CFG_KEY_REG_BASE_ADDR 0xF0100000
315 #define CFG_IR_REG_BASE_ADDR 0xF0200000
316 #define CFG_FPGA_REG_BASE_ADDR 0xF0300000
318 /*-----------------------------------------------------------------------
319 * Definitions for initial stack pointer and data area
321 #define CFG_INIT_DCACHE_CS 4 /* use cs # 4 for data cache memory */
323 #define CFG_INIT_RAM_ADDR 0x40000000 /* inside of SDRAM */
324 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
325 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
326 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
327 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
329 /*-----------------------------------------------------------------------
330 * Definitions for Serial Presence Detect EEPROM address
331 * (to get SDRAM settings)
333 #define SPD_EEPROM_ADDRESS 0x50
336 * Internal Definitions
340 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
341 #define BOOTFLAG_WARM 0x02 /* Software reboot */
343 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
344 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
345 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
347 #endif /* __CONFIG_H */