2 * Configuation settings for the WB50N CPU Module.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/hardware.h>
12 /* ARM asynchronous clock */
13 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768
14 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
16 #define CONFIG_ARCH_CPU_INIT
18 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
19 #define CONFIG_SETUP_MEMORY_TAGS
20 #define CONFIG_INITRD_TAG
22 #ifndef CONFIG_SPL_BUILD
23 #define CONFIG_SKIP_LOWLEVEL_INIT
26 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
27 #define CONFIG_IMAGE_FORMAT_LEGACY
29 /* general purpose I/O */
30 #define CONFIG_AT91_GPIO
33 #define CONFIG_ATMEL_USART
34 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
35 #define CONFIG_USART_ID ATMEL_ID_DBGU
40 #define CONFIG_BOOTP_BOOTFILESIZE
41 #define CONFIG_BOOTP_BOOTPATH
42 #define CONFIG_BOOTP_GATEWAY
43 #define CONFIG_BOOTP_HOSTNAME
46 #define CONFIG_NR_DRAM_BANKS 1
47 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
48 #define CONFIG_SYS_SDRAM_SIZE 0x04000000
50 #ifdef CONFIG_SPL_BUILD
51 #define CONFIG_SYS_INIT_SP_ADDR 0x310000
53 #define CONFIG_SYS_INIT_SP_ADDR \
54 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
57 #define CONFIG_SYS_MEMTEST_START 0x21000000
58 #define CONFIG_SYS_MEMTEST_END 0x22000000
59 #define CONFIG_SYS_ALT_MEMTEST
62 #define CONFIG_NAND_ATMEL
63 #define CONFIG_SYS_MAX_NAND_DEVICE 1
64 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
66 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
68 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
69 #define CONFIG_SYS_NAND_ONFI_DETECTION
70 /* PMECC & PMERRLOC */
71 #define CONFIG_ATMEL_NAND_HWECC
72 #define CONFIG_ATMEL_NAND_HW_PMECC
73 #define CONFIG_PMECC_CAP 8
74 #define CONFIG_PMECC_SECTOR_SIZE 512
76 /* Ethernet Hardware */
79 #define CONFIG_NET_RETRY_COUNT 20
80 #define CONFIG_MACB_SEARCH_PHY
82 #define CONFIG_ETHADDR C0:EE:40:00:00:00
83 #define CONFIG_ENV_OVERWRITE 1
85 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
87 #define CONFIG_EXTRA_ENV_SETTINGS \
91 /* bootstrap + u-boot + env in nandflash */
92 #define CONFIG_ENV_OFFSET 0xA0000
93 #define CONFIG_ENV_OFFSET_REDUND 0xC0000
94 #define CONFIG_ENV_SIZE 0x20000
95 #define CONFIG_BOOTCOMMAND \
96 "nand read 0x22000000 0x000e0000 0x500000; " \
99 #define CONFIG_BOOTARGS \
100 "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
102 #define CONFIG_BAUDRATE 115200
104 #define CONFIG_SYS_CBSIZE 1024
105 #define CONFIG_SYS_MAXARGS 16
106 #define CONFIG_SYS_PBSIZE \
107 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
108 #define CONFIG_SYS_LONGHELP
109 #define CONFIG_CMDLINE_EDITING
110 #define CONFIG_AUTO_COMPLETE
112 /* Size of malloc() pool */
113 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
116 #define CONFIG_SPL_TEXT_BASE 0x300000
117 #define CONFIG_SPL_MAX_SIZE 0x10000
118 #define CONFIG_SPL_BSS_START_ADDR 0x20000000
119 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
120 #define CONFIG_SYS_SPL_MALLOC_START 0x20080000
121 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
123 #define CONFIG_SYS_MONITOR_LEN (512 << 10)
125 #define CONFIG_SPL_NAND_DRIVERS
126 #define CONFIG_SPL_NAND_BASE
127 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
128 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
129 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800
130 #define CONFIG_SYS_NAND_PAGE_COUNT 64
131 #define CONFIG_SYS_NAND_OOBSIZE 64
132 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
133 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
134 #define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER