2 * WORK Microwave work_92105 board configuration file
4 * (C) Copyright 2014 DENX Software Engineering GmbH
5 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __CONFIG_WORK_92105_H__
11 #define __CONFIG_WORK_92105_H__
13 /* SoC and board defines */
14 #include <linux/sizes.h>
15 #include <asm/arch/cpu.h>
18 * Define work_92105 machine type by hand -- done only for compatibility
19 * with original board code
21 #define CONFIG_MACH_TYPE 736
23 #define CONFIG_SYS_ICACHE_OFF
24 #define CONFIG_SYS_DCACHE_OFF
25 #if !defined(CONFIG_SPL_BUILD)
26 #define CONFIG_SKIP_LOWLEVEL_INIT
28 #define CONFIG_BOARD_EARLY_INIT_R
30 /* generate LPC32XX-specific SPL image */
31 #define CONFIG_LPC32XX_SPL
34 * Memory configurations
36 #define CONFIG_NR_DRAM_BANKS 1
37 #define CONFIG_SYS_MALLOC_LEN SZ_1M
38 #define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
39 #define CONFIG_SYS_SDRAM_SIZE SZ_128M
40 #define CONFIG_SYS_TEXT_BASE 0x80100000
41 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
42 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
44 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
46 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \
47 - GENERATED_GBL_DATA_SIZE)
52 #define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */
58 #define CONFIG_PHY_SMSC
59 #define CONFIG_LPC32XX_ETH
60 #define CONFIG_PHY_ADDR 0
61 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
62 /* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
68 #define CONFIG_SYS_I2C_LPC32XX
69 #define CONFIG_SYS_I2C
70 #define CONFIG_SYS_I2C_SPEED 350000
76 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x56
77 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
83 #define CONFIG_RTC_DS1374
86 * U-Boot General Configurations
88 #define CONFIG_SYS_LONGHELP
89 #define CONFIG_SYS_CBSIZE 1024
90 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
92 #define CONFIG_AUTO_COMPLETE
93 #define CONFIG_CMDLINE_EDITING
96 * NAND chip timings for FIXME: which one?
99 #define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
100 #define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
101 #define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818
102 #define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000
103 #define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545
104 #define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000
105 #define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333
111 /* driver configuration */
112 #define CONFIG_SYS_NAND_SELF_INIT
113 #define CONFIG_SYS_MAX_NAND_DEVICE 1
114 #define CONFIG_SYS_MAX_NAND_CHIPS 1
115 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
116 #define CONFIG_NAND_LPC32XX_MLC
122 #define CONFIG_LPC32XX_GPIO
128 #define CONFIG_LPC32XX_SSP
129 #define CONFIG_LPC32XX_SSP_TIMEOUT 100000
134 #define CONFIG_ENV_SIZE 0x00020000
135 #define CONFIG_ENV_OFFSET 0x00100000
136 #define CONFIG_ENV_OFFSET_REDUND 0x00120000
137 #define CONFIG_ENV_ADDR 0x80000100
142 #define CONFIG_CMDLINE_TAG
143 #define CONFIG_SETUP_MEMORY_TAGS
144 #define CONFIG_INITRD_TAG
146 #define CONFIG_BOOTFILE "uImage"
147 #define CONFIG_LOADADDR 0x80008000
153 /* SPL will be executed at offset 0 */
154 #define CONFIG_SPL_TEXT_BASE 0x00000000
155 /* SPL will use SRAM as stack */
156 #define CONFIG_SPL_STACK 0x0000FFF8
157 /* Use the framework and generic lib */
158 #define CONFIG_SPL_FRAMEWORK
159 /* SPL will use serial */
160 /* SPL will load U-Boot from NAND offset 0x40000 */
161 #define CONFIG_SPL_NAND_DRIVERS
162 #define CONFIG_SPL_NAND_BASE
163 #define CONFIG_SPL_NAND_BOOT
164 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
165 #define CONFIG_SPL_PAD_TO 0x20000
166 /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
167 #define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */
168 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
169 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
172 * Include SoC specific configuration
174 #include <asm/arch/config.h>
176 #endif /* __CONFIG_WORK_92105_H__*/