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   1 /*
   2  * Configuration for Xilinx ZynqMP emulation platforms
   3  *
   4  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   5  * Michal Simek <michal.simek@xilinx.com>
   6  * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
   7  *
   8  * Based on Configuration for Versatile Express
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __CONFIG_ZYNQMP_EP_H
  14 #define __CONFIG_ZYNQMP_EP_H
  15
  16 #define CONFIG_ZYNQ_SDHCI_MAX_FREQ      52000000
  17 #define CONFIG_ZYNQ_SDHCI_MIN_FREQ      (CONFIG_ZYNQ_SDHCI_MAX_FREQ << 9)
  18 #define CONFIG_ZYNQ_EEPROM
  19 #define CONFIG_AHCI
  20 #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \
  21                                  ZYNQMP_USB1_XHCI_BASEADDR}
  22
  23 #define COUNTER_FREQUENCY       4000000
  24
  25 #define CONFIG_KERNEL_FDT_OFST_SIZE \
  26         "kernel_offset=0x400000\0" \
  27         "fdt_offset=0x2400000\0" \
  28         "kernel_size=0x2000000\0" \
  29         "fdt_size=0x80000\0" \
  30         "board=ep108\0"
  31
  32 #include <configs/xilinx_zynqmp.h>
  33
  34 #endif /* __CONFIG_ZYNQMP_EP_H */