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1 /*
2  * Copyright 2008 Extreme Engineering Solutions, Inc.
3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 /*
9  * xpedite537x board configuration file
10  */
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /*
15  * High Level Configuration Options
16  */
17 #define CONFIG_BOOKE            1       /* BOOKE */
18 #define CONFIG_E500             1       /* BOOKE e500 family */
19 #define CONFIG_MPC8572          1
20 #define CONFIG_XPEDITE5370      1
21 #define CONFIG_SYS_BOARD_NAME   "XPedite5370"
22 #define CONFIG_SYS_FORM_3U_VPX  1
23 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_pre_init */
24 #define CONFIG_DISPLAY_BOARDINFO
25
26 #ifndef CONFIG_SYS_TEXT_BASE
27 #define CONFIG_SYS_TEXT_BASE    0xfff80000
28 #endif
29
30 #define CONFIG_PCI              1       /* Enable PCI/PCIE */
31 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play */
32 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
33 #define CONFIG_PCIE1            1       /* PCIE controler 1 */
34 #define CONFIG_PCIE2            1       /* PCIE controler 2 */
35 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
36 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
37 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
38 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
39 #define CONFIG_FSL_LAW          1       /* Use common FSL init code */
40 #define CONFIG_FSL_ELBC         1
41
42 /*
43  * Multicore config
44  */
45 #define CONFIG_MP
46 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
47 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
48
49 /*
50  * DDR config
51  */
52 #define CONFIG_SYS_FSL_DDR2
53 #undef CONFIG_FSL_DDR_INTERACTIVE
54 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
55 #define CONFIG_DDR_SPD
56 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
57 #define SPD_EEPROM_ADDRESS1             0x54    /* Both channels use the */
58 #define SPD_EEPROM_ADDRESS2             0x54    /* same SPD data         */
59 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
60 #define CONFIG_NUM_DDR_CONTROLLERS      2
61 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
62 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
63 #define CONFIG_DDR_ECC
64 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
65 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
66 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
67 #define CONFIG_VERY_BIG_RAM
68
69 #ifndef __ASSEMBLY__
70 extern unsigned long get_board_sys_clk(unsigned long dummy);
71 extern unsigned long get_board_ddr_clk(unsigned long dummy);
72 #endif
73
74 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
75 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
76
77 /*
78  * These can be toggled for performance analysis, otherwise use default.
79  */
80 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
81 #define CONFIG_BTB                      /* toggle branch predition */
82 #define CONFIG_ENABLE_36BIT_PHYS        1
83
84 #define CONFIG_SYS_CCSRBAR              0xef000000
85 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
86
87 /*
88  * Diagnostics
89  */
90 #define CONFIG_SYS_ALT_MEMTEST
91 #define CONFIG_SYS_MEMTEST_START        0x10000000
92 #define CONFIG_SYS_MEMTEST_END          0x20000000
93 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
94                                          CONFIG_SYS_POST_I2C)
95 #define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_DS1621_ADDR,    \
96                                          CONFIG_SYS_I2C_DS4510_ADDR,    \
97                                          CONFIG_SYS_I2C_EEPROM_ADDR,    \
98                                          CONFIG_SYS_I2C_LM90_ADDR,      \
99                                          CONFIG_SYS_I2C_PCA953X_ADDR0,  \
100                                          CONFIG_SYS_I2C_PCA953X_ADDR1,  \
101                                          CONFIG_SYS_I2C_PCA953X_ADDR2,  \
102                                          CONFIG_SYS_I2C_PCA953X_ADDR3,  \
103                                          CONFIG_SYS_I2C_PEX8518_ADDR,   \
104                                          CONFIG_SYS_I2C_RTC_ADDR}
105 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
106 #define I2C_ADDR_IGNORE_LIST            {0x50}
107
108 /*
109  * Memory map
110  * 0x0000_0000  0x7fff_ffff     DDR                     2G Cacheable
111  * 0x8000_0000  0xbfff_ffff     PCIe1 Mem               1G non-cacheable
112  * 0xc000_0000  0xcfff_ffff     PCIe2 Mem               256M non-cacheable
113  * 0xe000_0000  0xe7ff_ffff     SRAM/SSRAM/L1 Cache     128M non-cacheable
114  * 0xe800_0000  0xe87f_ffff     PCIe1 IO                8M non-cacheable
115  * 0xe880_0000  0xe8ff_ffff     PCIe2 IO                8M non-cacheable
116  * 0xee00_0000  0xee00_ffff     Boot page translation   4K non-cacheable
117  * 0xef00_0000  0xef0f_ffff     CCSR/IMMR               1M non-cacheable
118  * 0xef80_0000  0xef8f_ffff     NAND Flash              1M non-cacheable
119  * 0xf000_0000  0xf7ff_ffff     NOR Flash 2             128M non-cacheable
120  * 0xf800_0000  0xffff_ffff     NOR Flash 1             128M non-cacheable
121  */
122
123 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
124
125 /*
126  * NAND flash configuration
127  */
128 #define CONFIG_SYS_NAND_BASE            0xef800000
129 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
130 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
131                                          CONFIG_SYS_NAND_BASE2}
132 #define CONFIG_SYS_MAX_NAND_DEVICE      2
133 #define CONFIG_NAND_FSL_ELBC
134
135 /*
136  * NOR flash configuration
137  */
138 #define CONFIG_SYS_FLASH_BASE           0xf8000000
139 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
140 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
141 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
142 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
143 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
144 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
145 #define CONFIG_FLASH_CFI_DRIVER
146 #define CONFIG_SYS_FLASH_CFI
147 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
148 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
149                                                   {0xf7f40000, 0xc0000} }
150 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
151
152 /*
153  * Chip select configuration
154  */
155 /* NOR Flash 0 on CS0 */
156 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
157                                  BR_PS_16               | \
158                                  BR_V)
159 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
160                                  OR_GPCM_CSNT           | \
161                                  OR_GPCM_XACS           | \
162                                  OR_GPCM_ACS_DIV2       | \
163                                  OR_GPCM_SCY_8          | \
164                                  OR_GPCM_TRLX           | \
165                                  OR_GPCM_EHTR           | \
166                                  OR_GPCM_EAD)
167
168 /* NOR Flash 1 on CS1 */
169 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
170                                  BR_PS_16               | \
171                                  BR_V)
172 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
173
174 /* NAND flash on CS2 */
175 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
176                                  (2<<BR_DECC_SHIFT)     | \
177                                  BR_PS_8                | \
178                                  BR_MS_FCM              | \
179                                  BR_V)
180
181 /* NAND flash on CS2 */
182 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
183                                  OR_FCM_PGS     | \
184                                  OR_FCM_CSCT    | \
185                                  OR_FCM_CST     | \
186                                  OR_FCM_CHT     | \
187                                  OR_FCM_SCY_1   | \
188                                  OR_FCM_TRLX    | \
189                                  OR_FCM_EHTR)
190
191 /* NAND flash on CS3 */
192 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
193                                  (2<<BR_DECC_SHIFT)     | \
194                                  BR_PS_8                | \
195                                  BR_MS_FCM              | \
196                                  BR_V)
197 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
198
199 /*
200  * Use L1 as initial stack
201  */
202 #define CONFIG_SYS_INIT_RAM_LOCK        1
203 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
204 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
205
206 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
207 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
208
209 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
210 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
211
212 /*
213  * Serial Port
214  */
215 #define CONFIG_CONS_INDEX               1
216 #define CONFIG_SYS_NS16550_SERIAL
217 #define CONFIG_SYS_NS16550_REG_SIZE     1
218 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
219 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
220 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
221 #define CONFIG_SYS_BAUDRATE_TABLE       \
222         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
223 #define CONFIG_BAUDRATE                 115200
224 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
225 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
226
227 /*
228  * I2C
229  */
230 #define CONFIG_SYS_I2C
231 #define CONFIG_SYS_I2C_FSL
232 #define CONFIG_SYS_FSL_I2C_SPEED        400000
233 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
234 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
235 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
236 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
237 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
238 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
239
240 /* PEX8518 slave I2C interface */
241 #define CONFIG_SYS_I2C_PEX8518_ADDR     0x70
242
243 /* I2C DS1631 temperature sensor */
244 #define CONFIG_SYS_I2C_DS1621_ADDR      0x48
245 #define CONFIG_DTT_DS1621
246 #define CONFIG_DTT_SENSORS              { 0 }
247 #define CONFIG_SYS_I2C_LM90_ADDR        0x4c
248
249 /* I2C EEPROM - AT24C128B */
250 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
254
255 /* I2C RTC */
256 #define CONFIG_RTC_M41T11               1
257 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
258 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
259
260 /* GPIO/EEPROM/SRAM */
261 #define CONFIG_DS4510
262 #define CONFIG_SYS_I2C_DS4510_ADDR      0x51
263
264 /* GPIO */
265 #define CONFIG_PCA953X
266 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
267 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
268 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
269 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
270 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
271
272 /*
273  * PU = pulled high, PD = pulled low
274  * I = input, O = output, IO = input/output
275  */
276 /* PCA9557 @ 0x18*/
277 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
278 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select */
279 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
280 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select */
281 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
282 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Set to 0 to enable NVM writing */
283 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2        0x40 /* VID2 of ISL6262 */
284 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3        0x80 /* VID3 of ISL6262 */
285
286 /* PCA9557 @ 0x1c*/
287 #define CONFIG_SYS_PCA953X_XMC0_ROOT0           0x01 /* PU; Low if XMC is RC */
288 #define CONFIG_SYS_PCA953X_XMC0_MVMR0           0x02 /* XMC EEPROM write protect */
289 #define CONFIG_SYS_PCA953X_XMC0_WAKE            0x04 /* PU; XMC wake */
290 #define CONFIG_SYS_PCA953X_XMC0_BIST            0x08 /* PU; XMC built in self test */
291 #define CONFIG_SYS_PCA953X_XMC_PRESENT          0x10 /* PU; Low if XMC module installed */
292 #define CONFIG_SYS_PCA953X_PMC_PRESENT          0x20 /* PU; Low if PMC module installed */
293 #define CONFIG_SYS_PCA953X_PMC0_MONARCH         0x40 /* PMC monarch mode enable */
294 #define CONFIG_SYS_PCA953X_PMC0_EREADY          0x80 /* PU; PMC PCI eready */
295
296 /* PCA9557 @ 0x1e*/
297 #define CONFIG_SYS_PCA953X_P0_GA0               0x01 /* PU; VPX Geographical address */
298 #define CONFIG_SYS_PCA953X_P0_GA1               0x02 /* PU; VPX Geographical address */
299 #define CONFIG_SYS_PCA953X_P0_GA2               0x04 /* PU; VPX Geographical address */
300 #define CONFIG_SYS_PCA953X_P0_GA3               0x08 /* PU; VPX Geographical address */
301 #define CONFIG_SYS_PCA953X_P0_GA4               0x10 /* PU; VPX Geographical address */
302 #define CONFIG_SYS_PCA953X_P0_GAP               0x20 /* PU; tied to VPX P0.GAP */
303 #define CONFIG_SYS_PCA953X_P1_SYSEN             0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
304
305 /* PCA9557 @ 0x1f */
306 #define CONFIG_SYS_PCA953X_GPIO_VPX0            0x01 /* PU */
307 #define CONFIG_SYS_PCA953X_GPIO_VPX1            0x02 /* PU */
308 #define CONFIG_SYS_PCA953X_GPIO_VPX2            0x04 /* PU */
309 #define CONFIG_SYS_PCA953X_GPIO_VPX3            0x08 /* PU */
310 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL        0x10 /* PD; I2C master source for FRU SEEPROM */
311
312 /*
313  * General PCI
314  * Memory space is mapped 1-1, but I/O space must start from 0.
315  */
316 /* PCIE1 - VPX P1 */
317 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
318 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
319 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
320 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
321 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
322 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
323
324 /* PCIE2 - PEX8518 */
325 #define CONFIG_SYS_PCIE2_MEM_BUS        0xc0000000
326 #define CONFIG_SYS_PCIE2_MEM_PHYS       CONFIG_SYS_PCIE2_MEM_BUS
327 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000      /* 256M */
328 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
329 #define CONFIG_SYS_PCIE2_IO_PHYS        0xe8800000
330 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00800000      /* 8M */
331
332 /*
333  * Networking options
334  */
335 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
336 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
337 #define CONFIG_TSEC_TBI
338 #define CONFIG_MII              1       /* MII PHY management */
339 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
340 #define CONFIG_ETHPRIME         "eTSEC2"
341
342 /*
343  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
344  * 1000mbps SGMII link
345  */
346 #define CONFIG_TSEC_TBICR_SETTINGS ( \
347                 TBICR_PHY_RESET \
348                 | TBICR_FULL_DUPLEX \
349                 | TBICR_SPEED1_SET \
350                 )
351
352 #define CONFIG_TSEC1            1
353 #define CONFIG_TSEC1_NAME       "eTSEC1"
354 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
355 #define TSEC1_PHY_ADDR          1
356 #define TSEC1_PHYIDX            0
357 #define CONFIG_HAS_ETH0
358
359 #define CONFIG_TSEC2            1
360 #define CONFIG_TSEC2_NAME       "eTSEC2"
361 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
362 #define TSEC2_PHY_ADDR          2
363 #define TSEC2_PHYIDX            0
364 #define CONFIG_HAS_ETH1
365
366 /*
367  * Command configuration.
368  */
369 #define CONFIG_CMD_ASKENV
370 #define CONFIG_CMD_DATE
371 #define CONFIG_CMD_DS4510
372 #define CONFIG_CMD_DS4510_INFO
373 #define CONFIG_CMD_DTT
374 #define CONFIG_CMD_EEPROM
375 #define CONFIG_CMD_JFFS2
376 #define CONFIG_CMD_MII
377 #define CONFIG_CMD_NAND
378 #define CONFIG_CMD_PCA953X
379 #define CONFIG_CMD_PCA953X_INFO
380 #define CONFIG_CMD_PCI
381 #define CONFIG_CMD_PCI_ENUM
382 #define CONFIG_CMD_REGINFO
383
384 /*
385  * Miscellaneous configurable options
386  */
387 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
388 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
389 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
390 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
391 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
392 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
393 #define CONFIG_CMDLINE_EDITING  1               /* add command line history     */
394 #define CONFIG_AUTO_COMPLETE    1               /* add autocompletion support */
395 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
396 #define CONFIG_BOOTDELAY        3               /* -1 disables auto-boot */
397 #define CONFIG_PANIC_HANG                       /* do not reset board on panic */
398 #define CONFIG_PREBOOT                          /* enable preboot variable */
399 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
400
401 /*
402  * For booting Linux, the board info and command line data
403  * have to be in the first 16 MB of memory, since this is
404  * the maximum mapped by the Linux kernel during initialization.
405  */
406 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
407 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
408
409 /*
410  * Environment Configuration
411  */
412 #define CONFIG_ENV_IS_IN_FLASH  1
413 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
414 #define CONFIG_ENV_SIZE         0x8000
415 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
416
417 /*
418  * Flash memory map:
419  * fff80000 - ffffffff     Pri U-Boot (512 KB)
420  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
421  * fff00000 - fff3ffff     Pri FDT (256KB)
422  * fef00000 - ffefffff     Pri OS image (16MB)
423  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
424  *
425  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
426  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
427  * f7f00000 - f7f3ffff     Sec FDT (256KB)
428  * f6f00000 - f7efffff     Sec OS image (16MB)
429  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
430  */
431 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
432 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
433 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
434 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
435 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
436 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
437
438 #define CONFIG_PROG_UBOOT1                                              \
439         "$download_cmd $loadaddr $ubootfile; "                          \
440         "if test $? -eq 0; then "                                       \
441                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
442                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
443                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
444                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
445                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
446                 "if test $? -ne 0; then "                               \
447                         "echo PROGRAM FAILED; "                         \
448                 "else; "                                                \
449                         "echo PROGRAM SUCCEEDED; "                      \
450                 "fi; "                                                  \
451         "else; "                                                        \
452                 "echo DOWNLOAD FAILED; "                                \
453         "fi;"
454
455 #define CONFIG_PROG_UBOOT2                                              \
456         "$download_cmd $loadaddr $ubootfile; "                          \
457         "if test $? -eq 0; then "                                       \
458                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
459                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
460                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
461                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
462                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
463                 "if test $? -ne 0; then "                               \
464                         "echo PROGRAM FAILED; "                         \
465                 "else; "                                                \
466                         "echo PROGRAM SUCCEEDED; "                      \
467                 "fi; "                                                  \
468         "else; "                                                        \
469                 "echo DOWNLOAD FAILED; "                                \
470         "fi;"
471
472 #define CONFIG_BOOT_OS_NET                                              \
473         "$download_cmd $osaddr $osfile; "                               \
474         "if test $? -eq 0; then "                                       \
475                 "if test -n $fdtaddr; then "                            \
476                         "$download_cmd $fdtaddr $fdtfile; "             \
477                         "if test $? -eq 0; then "                       \
478                                 "bootm $osaddr - $fdtaddr; "            \
479                         "else; "                                        \
480                                 "echo FDT DOWNLOAD FAILED; "            \
481                         "fi; "                                          \
482                 "else; "                                                \
483                         "bootm $osaddr; "                               \
484                 "fi; "                                                  \
485         "else; "                                                        \
486                 "echo OS DOWNLOAD FAILED; "                             \
487         "fi;"
488
489 #define CONFIG_PROG_OS1                                                 \
490         "$download_cmd $osaddr $osfile; "                               \
491         "if test $? -eq 0; then "                                       \
492                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
493                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
494                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
495                 "if test $? -ne 0; then "                               \
496                         "echo OS PROGRAM FAILED; "                      \
497                 "else; "                                                \
498                         "echo OS PROGRAM SUCCEEDED; "                   \
499                 "fi; "                                                  \
500         "else; "                                                        \
501                 "echo OS DOWNLOAD FAILED; "                             \
502         "fi;"
503
504 #define CONFIG_PROG_OS2                                                 \
505         "$download_cmd $osaddr $osfile; "                               \
506         "if test $? -eq 0; then "                                       \
507                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
508                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
509                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
510                 "if test $? -ne 0; then "                               \
511                         "echo OS PROGRAM FAILED; "                      \
512                 "else; "                                                \
513                         "echo OS PROGRAM SUCCEEDED; "                   \
514                 "fi; "                                                  \
515         "else; "                                                        \
516                 "echo OS DOWNLOAD FAILED; "                             \
517         "fi;"
518
519 #define CONFIG_PROG_FDT1                                                \
520         "$download_cmd $fdtaddr $fdtfile; "                             \
521         "if test $? -eq 0; then "                                       \
522                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
523                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
524                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
525                 "if test $? -ne 0; then "                               \
526                         "echo FDT PROGRAM FAILED; "                     \
527                 "else; "                                                \
528                         "echo FDT PROGRAM SUCCEEDED; "                  \
529                 "fi; "                                                  \
530         "else; "                                                        \
531                 "echo FDT DOWNLOAD FAILED; "                            \
532         "fi;"
533
534 #define CONFIG_PROG_FDT2                                                \
535         "$download_cmd $fdtaddr $fdtfile; "                             \
536         "if test $? -eq 0; then "                                       \
537                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
538                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
539                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
540                 "if test $? -ne 0; then "                               \
541                         "echo FDT PROGRAM FAILED; "                     \
542                 "else; "                                                \
543                         "echo FDT PROGRAM SUCCEEDED; "                  \
544                 "fi; "                                                  \
545         "else; "                                                        \
546                 "echo FDT DOWNLOAD FAILED; "                            \
547         "fi;"
548
549 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
550         "autoload=yes\0"                                                \
551         "download_cmd=tftp\0"                                           \
552         "console_args=console=ttyS0,115200\0"                           \
553         "root_args=root=/dev/nfs rw\0"                                  \
554         "misc_args=ip=on\0"                                             \
555         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
556         "bootfile=/home/user/file\0"                                    \
557         "osfile=/home/user/board.uImage\0"                              \
558         "fdtfile=/home/user/board.dtb\0"                                \
559         "ubootfile=/home/user/u-boot.bin\0"                             \
560         "fdtaddr=c00000\0"                                              \
561         "osaddr=0x1000000\0"                                            \
562         "loadaddr=0x1000000\0"                                          \
563         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
564         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
565         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
566         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
567         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
568         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
569         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
570         "bootcmd_flash1=run set_bootargs; "                             \
571                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
572         "bootcmd_flash2=run set_bootargs; "                             \
573                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
574         "bootcmd=run bootcmd_flash1\0"
575 #endif  /* __CONFIG_H */