2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 * xpedite537x board configuration file
15 * High Level Configuration Options
17 #define CONFIG_BOOKE 1 /* BOOKE */
18 #define CONFIG_E500 1 /* BOOKE e500 family */
19 #define CONFIG_SYS_BOARD_NAME "XPedite5370"
20 #define CONFIG_SYS_FORM_3U_VPX 1
21 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
23 #ifndef CONFIG_SYS_TEXT_BASE
24 #define CONFIG_SYS_TEXT_BASE 0xfff80000
27 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
28 #define CONFIG_PCIE1 1 /* PCIE controller 1 */
29 #define CONFIG_PCIE2 1 /* PCIE controller 2 */
30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
32 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
33 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
34 #define CONFIG_FSL_ELBC 1
40 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
41 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
46 #define CONFIG_SYS_FSL_DDR2
47 #undef CONFIG_FSL_DDR_INTERACTIVE
48 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
49 #define CONFIG_DDR_SPD
50 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
51 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
52 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
53 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
54 #define CONFIG_NUM_DDR_CONTROLLERS 2
55 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
56 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
57 #define CONFIG_DDR_ECC
58 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
59 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
60 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
61 #define CONFIG_VERY_BIG_RAM
64 extern unsigned long get_board_sys_clk(unsigned long dummy);
65 extern unsigned long get_board_ddr_clk(unsigned long dummy);
68 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
69 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
72 * These can be toggled for performance analysis, otherwise use default.
74 #define CONFIG_L2_CACHE /* toggle L2 cache */
75 #define CONFIG_BTB /* toggle branch predition */
76 #define CONFIG_ENABLE_36BIT_PHYS 1
78 #define CONFIG_SYS_CCSRBAR 0xef000000
79 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
84 #define CONFIG_SYS_ALT_MEMTEST
85 #define CONFIG_SYS_MEMTEST_START 0x10000000
86 #define CONFIG_SYS_MEMTEST_END 0x20000000
87 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
89 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
90 CONFIG_SYS_I2C_DS4510_ADDR, \
91 CONFIG_SYS_I2C_EEPROM_ADDR, \
92 CONFIG_SYS_I2C_LM90_ADDR, \
93 CONFIG_SYS_I2C_PCA953X_ADDR0, \
94 CONFIG_SYS_I2C_PCA953X_ADDR1, \
95 CONFIG_SYS_I2C_PCA953X_ADDR2, \
96 CONFIG_SYS_I2C_PCA953X_ADDR3, \
97 CONFIG_SYS_I2C_PEX8518_ADDR, \
98 CONFIG_SYS_I2C_RTC_ADDR}
99 /* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
100 #define I2C_ADDR_IGNORE_LIST {0x50}
104 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
105 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
106 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
107 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
108 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
109 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
110 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
111 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
112 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
113 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
114 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
117 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
120 * NAND flash configuration
122 #define CONFIG_SYS_NAND_BASE 0xef800000
123 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
124 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
125 CONFIG_SYS_NAND_BASE2}
126 #define CONFIG_SYS_MAX_NAND_DEVICE 2
127 #define CONFIG_NAND_FSL_ELBC
130 * NOR flash configuration
132 #define CONFIG_SYS_FLASH_BASE 0xf8000000
133 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
134 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
135 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
136 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
137 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
139 #define CONFIG_FLASH_CFI_DRIVER
140 #define CONFIG_SYS_FLASH_CFI
141 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
142 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
143 {0xf7f40000, 0xc0000} }
144 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
147 * Chip select configuration
149 /* NOR Flash 0 on CS0 */
150 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
153 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
162 /* NOR Flash 1 on CS1 */
163 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
166 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
168 /* NAND flash on CS2 */
169 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
170 (2<<BR_DECC_SHIFT) | \
175 /* NAND flash on CS2 */
176 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
185 /* NAND flash on CS3 */
186 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
187 (2<<BR_DECC_SHIFT) | \
191 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
194 * Use L1 as initial stack
196 #define CONFIG_SYS_INIT_RAM_LOCK 1
197 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
198 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
200 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
201 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
203 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
204 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
209 #define CONFIG_CONS_INDEX 1
210 #define CONFIG_SYS_NS16550_SERIAL
211 #define CONFIG_SYS_NS16550_REG_SIZE 1
212 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
213 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
214 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
215 #define CONFIG_SYS_BAUDRATE_TABLE \
216 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
217 #define CONFIG_BAUDRATE 115200
218 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
219 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
224 #define CONFIG_SYS_I2C
225 #define CONFIG_SYS_I2C_FSL
226 #define CONFIG_SYS_FSL_I2C_SPEED 400000
227 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
228 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
229 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
230 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
231 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
232 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
234 /* PEX8518 slave I2C interface */
235 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
237 /* I2C DS1631 temperature sensor */
238 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
239 #define CONFIG_DTT_DS1621
240 #define CONFIG_DTT_SENSORS { 0 }
241 #define CONFIG_SYS_I2C_LM90_ADDR 0x4c
243 /* I2C EEPROM - AT24C128B */
244 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
245 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
247 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
250 #define CONFIG_RTC_M41T11 1
251 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
252 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
254 /* GPIO/EEPROM/SRAM */
255 #define CONFIG_DS4510
256 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
259 #define CONFIG_PCA953X
260 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
261 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
262 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
263 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
264 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
267 * PU = pulled high, PD = pulled low
268 * I = input, O = output, IO = input/output
271 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
272 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
273 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
274 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
275 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
276 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
277 #define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
278 #define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
281 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
282 #define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
283 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
284 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
285 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
286 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
287 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
288 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
291 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
292 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
293 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
294 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
295 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
296 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
297 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
300 #define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
301 #define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
302 #define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
303 #define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
304 #define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
308 * Memory space is mapped 1-1, but I/O space must start from 0.
311 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
312 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
313 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
314 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
315 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
316 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
318 /* PCIE2 - PEX8518 */
319 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
320 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
321 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
322 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
323 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
324 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
329 #define CONFIG_TSEC_ENET /* tsec ethernet support */
330 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
331 #define CONFIG_TSEC_TBI
332 #define CONFIG_MII 1 /* MII PHY management */
333 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
334 #define CONFIG_ETHPRIME "eTSEC2"
337 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
338 * 1000mbps SGMII link
340 #define CONFIG_TSEC_TBICR_SETTINGS ( \
342 | TBICR_FULL_DUPLEX \
346 #define CONFIG_TSEC1 1
347 #define CONFIG_TSEC1_NAME "eTSEC1"
348 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
349 #define TSEC1_PHY_ADDR 1
350 #define TSEC1_PHYIDX 0
351 #define CONFIG_HAS_ETH0
353 #define CONFIG_TSEC2 1
354 #define CONFIG_TSEC2_NAME "eTSEC2"
355 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
356 #define TSEC2_PHY_ADDR 2
357 #define TSEC2_PHYIDX 0
358 #define CONFIG_HAS_ETH1
361 * Command configuration.
363 #define CONFIG_CMD_DATE
364 #define CONFIG_CMD_DS4510
365 #define CONFIG_CMD_DS4510_INFO
366 #define CONFIG_CMD_DTT
367 #define CONFIG_CMD_EEPROM
368 #define CONFIG_CMD_JFFS2
369 #define CONFIG_CMD_NAND
370 #define CONFIG_CMD_PCA953X
371 #define CONFIG_CMD_PCA953X_INFO
372 #define CONFIG_CMD_PCI
373 #define CONFIG_CMD_PCI_ENUM
374 #define CONFIG_CMD_REGINFO
377 * Miscellaneous configurable options
379 #define CONFIG_SYS_LONGHELP /* undef to save memory */
380 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
381 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
382 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
383 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
384 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
385 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
386 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
387 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
388 #define CONFIG_PANIC_HANG /* do not reset board on panic */
389 #define CONFIG_PREBOOT /* enable preboot variable */
390 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
393 * For booting Linux, the board info and command line data
394 * have to be in the first 16 MB of memory, since this is
395 * the maximum mapped by the Linux kernel during initialization.
397 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
398 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
401 * Environment Configuration
403 #define CONFIG_ENV_IS_IN_FLASH 1
404 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
405 #define CONFIG_ENV_SIZE 0x8000
406 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
410 * fff80000 - ffffffff Pri U-Boot (512 KB)
411 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
412 * fff00000 - fff3ffff Pri FDT (256KB)
413 * fef00000 - ffefffff Pri OS image (16MB)
414 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
416 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
417 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
418 * f7f00000 - f7f3ffff Sec FDT (256KB)
419 * f6f00000 - f7efffff Sec OS image (16MB)
420 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
422 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
423 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
424 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
425 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
426 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
427 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
429 #define CONFIG_PROG_UBOOT1 \
430 "$download_cmd $loadaddr $ubootfile; " \
431 "if test $? -eq 0; then " \
432 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
433 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
434 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
435 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
436 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
437 "if test $? -ne 0; then " \
438 "echo PROGRAM FAILED; " \
440 "echo PROGRAM SUCCEEDED; " \
443 "echo DOWNLOAD FAILED; " \
446 #define CONFIG_PROG_UBOOT2 \
447 "$download_cmd $loadaddr $ubootfile; " \
448 "if test $? -eq 0; then " \
449 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
450 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
451 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
452 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
453 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
454 "if test $? -ne 0; then " \
455 "echo PROGRAM FAILED; " \
457 "echo PROGRAM SUCCEEDED; " \
460 "echo DOWNLOAD FAILED; " \
463 #define CONFIG_BOOT_OS_NET \
464 "$download_cmd $osaddr $osfile; " \
465 "if test $? -eq 0; then " \
466 "if test -n $fdtaddr; then " \
467 "$download_cmd $fdtaddr $fdtfile; " \
468 "if test $? -eq 0; then " \
469 "bootm $osaddr - $fdtaddr; " \
471 "echo FDT DOWNLOAD FAILED; " \
477 "echo OS DOWNLOAD FAILED; " \
480 #define CONFIG_PROG_OS1 \
481 "$download_cmd $osaddr $osfile; " \
482 "if test $? -eq 0; then " \
483 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
484 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
485 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
486 "if test $? -ne 0; then " \
487 "echo OS PROGRAM FAILED; " \
489 "echo OS PROGRAM SUCCEEDED; " \
492 "echo OS DOWNLOAD FAILED; " \
495 #define CONFIG_PROG_OS2 \
496 "$download_cmd $osaddr $osfile; " \
497 "if test $? -eq 0; then " \
498 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
499 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
500 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
501 "if test $? -ne 0; then " \
502 "echo OS PROGRAM FAILED; " \
504 "echo OS PROGRAM SUCCEEDED; " \
507 "echo OS DOWNLOAD FAILED; " \
510 #define CONFIG_PROG_FDT1 \
511 "$download_cmd $fdtaddr $fdtfile; " \
512 "if test $? -eq 0; then " \
513 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
514 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
515 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
516 "if test $? -ne 0; then " \
517 "echo FDT PROGRAM FAILED; " \
519 "echo FDT PROGRAM SUCCEEDED; " \
522 "echo FDT DOWNLOAD FAILED; " \
525 #define CONFIG_PROG_FDT2 \
526 "$download_cmd $fdtaddr $fdtfile; " \
527 "if test $? -eq 0; then " \
528 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
529 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
530 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
531 "if test $? -ne 0; then " \
532 "echo FDT PROGRAM FAILED; " \
534 "echo FDT PROGRAM SUCCEEDED; " \
537 "echo FDT DOWNLOAD FAILED; " \
540 #define CONFIG_EXTRA_ENV_SETTINGS \
542 "download_cmd=tftp\0" \
543 "console_args=console=ttyS0,115200\0" \
544 "root_args=root=/dev/nfs rw\0" \
545 "misc_args=ip=on\0" \
546 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
547 "bootfile=/home/user/file\0" \
548 "osfile=/home/user/board.uImage\0" \
549 "fdtfile=/home/user/board.dtb\0" \
550 "ubootfile=/home/user/u-boot.bin\0" \
551 "fdtaddr=0x1e00000\0" \
552 "osaddr=0x1000000\0" \
553 "loadaddr=0x1000000\0" \
554 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
555 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
556 "prog_os1="CONFIG_PROG_OS1"\0" \
557 "prog_os2="CONFIG_PROG_OS2"\0" \
558 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
559 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
560 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
561 "bootcmd_flash1=run set_bootargs; " \
562 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
563 "bootcmd_flash2=run set_bootargs; " \
564 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
565 "bootcmd=run bootcmd_flash1\0"
566 #endif /* __CONFIG_H */