2 * Copyright 2010 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 * xpedite550x board configuration file
15 * High Level Configuration Options
17 #define CONFIG_SYS_BOARD_NAME "XPedite5500"
18 #define CONFIG_SYS_FORM_PMC_XMC 1
19 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
20 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
22 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
23 #define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
24 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
25 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
26 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
27 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
33 #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
34 #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
39 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
40 #define CONFIG_DDR_SPD
41 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
42 #define SPD_EEPROM_ADDRESS 0x54
43 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
44 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
45 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
46 #define CONFIG_DDR_ECC
47 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
48 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
49 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
50 #define CONFIG_VERY_BIG_RAM
53 extern unsigned long get_board_sys_clk(unsigned long dummy);
54 extern unsigned long get_board_ddr_clk(unsigned long dummy);
57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
58 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
61 * These can be toggled for performance analysis, otherwise use default.
63 #define CONFIG_L2_CACHE /* toggle L2 cache */
64 #define CONFIG_BTB /* toggle branch predition */
65 #define CONFIG_ENABLE_36BIT_PHYS 1
67 #define CONFIG_SYS_CCSRBAR 0xef000000
68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
73 #define CONFIG_SYS_ALT_MEMTEST
74 #define CONFIG_SYS_MEMTEST_START 0x10000000
75 #define CONFIG_SYS_MEMTEST_END 0x20000000
76 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
78 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
79 CONFIG_SYS_I2C_LM75_ADDR, \
80 CONFIG_SYS_I2C_LM90_ADDR, \
81 CONFIG_SYS_I2C_PCA953X_ADDR0, \
82 CONFIG_SYS_I2C_PCA953X_ADDR2, \
83 CONFIG_SYS_I2C_PCA953X_ADDR3, \
84 CONFIG_SYS_I2C_RTC_ADDR}
88 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
89 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
90 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
91 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
92 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
93 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
94 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
95 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
96 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
99 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
102 * NAND flash configuration
104 #define CONFIG_SYS_NAND_BASE 0xef800000
105 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
106 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
107 CONFIG_SYS_NAND_BASE2}
108 #define CONFIG_SYS_MAX_NAND_DEVICE 2
109 #define CONFIG_NAND_FSL_ELBC
112 * NOR flash configuration
114 #define CONFIG_SYS_FLASH_BASE 0xf8000000
115 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
116 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
117 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
118 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
119 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
120 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
121 #define CONFIG_FLASH_CFI_DRIVER
122 #define CONFIG_SYS_FLASH_CFI
123 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
124 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
125 {0xf7f40000, 0xc0000} }
126 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
129 * Chip select configuration
131 /* NOR Flash 0 on CS0 */
132 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
135 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
144 /* NOR Flash 1 on CS1 */
145 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
148 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
150 /* NAND flash on CS2 */
151 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
152 (2<<BR_DECC_SHIFT) | \
157 /* NAND flash on CS2 */
158 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
167 /* NAND flash on CS3 */
168 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
169 (2<<BR_DECC_SHIFT) | \
173 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
176 * Use L1 as initial stack
178 #define CONFIG_SYS_INIT_RAM_LOCK 1
179 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
180 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
182 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
183 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
185 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
186 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
191 #define CONFIG_SYS_NS16550_SERIAL
192 #define CONFIG_SYS_NS16550_REG_SIZE 1
193 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
194 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
195 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
196 #define CONFIG_SYS_BAUDRATE_TABLE \
197 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
198 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
199 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
205 #define CONFIG_SYS_I2C
206 #define CONFIG_SYS_I2C_FSL
207 #define CONFIG_SYS_FSL_I2C_SPEED 400000
208 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
209 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
210 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
211 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
212 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
214 /* I2C DS7505 temperature sensor */
215 #define CONFIG_SYS_I2C_LM75_ADDR 0x48
217 /* I2C ADT7461 temperature sensor */
218 #define CONFIG_SYS_I2C_LM90_ADDR 0x4C
220 /* I2C EEPROM - AT24C128B */
221 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
222 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
224 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
227 #define CONFIG_RTC_M41T11 1
228 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
229 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
232 #define CONFIG_PCA953X
233 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
234 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
235 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
236 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
237 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
240 * GPIO pin definitions, PU = pulled high, PD = pulled low
243 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
244 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
245 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
246 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
247 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
248 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
251 #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
252 #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
253 #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
254 #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
255 #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
256 #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
257 #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
260 #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
261 #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
262 #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
263 #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
264 #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
265 #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
266 #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
267 #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
271 * Memory space is mapped 1-1, but I/O space must start from 0.
274 /* controller 1 - PEX8112 or XMC, depending on build option */
275 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
276 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
277 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
278 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
279 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
280 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
285 #define CONFIG_TSEC_ENET /* tsec ethernet support */
286 #define CONFIG_TSEC_TBI
287 #define CONFIG_MII 1 /* MII PHY management */
288 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
289 #define CONFIG_ETHPRIME "eTSEC2"
292 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
293 * 1000mbps SGMII link
295 #define CONFIG_TSEC_TBICR_SETTINGS ( \
297 | TBICR_FULL_DUPLEX \
301 #define CONFIG_TSEC1 1
302 #define CONFIG_TSEC1_NAME "eTSEC1"
303 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
304 #define TSEC1_PHY_ADDR 1
305 #define TSEC1_PHYIDX 0
306 #define CONFIG_HAS_ETH0
308 #define CONFIG_TSEC2 1
309 #define CONFIG_TSEC2_NAME "eTSEC2"
310 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
311 #define TSEC2_PHY_ADDR 2
312 #define TSEC2_PHYIDX 0
313 #define CONFIG_HAS_ETH1
315 #define CONFIG_TSEC3 1
316 #define CONFIG_TSEC3_NAME "eTSEC3"
317 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
318 #define TSEC3_PHY_ADDR 3
319 #define TSEC3_PHYIDX 0
320 #define CONFIG_HAS_ETH2
325 #define CONFIG_USB_EHCI_FSL
326 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
329 * Miscellaneous configurable options
331 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
332 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
333 #define CONFIG_PREBOOT /* enable preboot variable */
334 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
337 * For booting Linux, the board info and command line data
338 * have to be in the first 16 MB of memory, since this is
339 * the maximum mapped by the Linux kernel during initialization.
341 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
342 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
345 * Environment Configuration
347 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
348 #define CONFIG_ENV_SIZE 0x8000
349 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
353 * fff80000 - ffffffff Pri U-Boot (512 KB)
354 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
355 * fff00000 - fff3ffff Pri FDT (256KB)
356 * fef00000 - ffefffff Pri OS image (16MB)
357 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
359 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
360 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
361 * f7f00000 - f7f3ffff Sec FDT (256KB)
362 * f6f00000 - f7efffff Sec OS image (16MB)
363 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
365 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
366 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
367 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
368 #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
369 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
370 #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
372 #define CONFIG_PROG_UBOOT1 \
373 "$download_cmd $loadaddr $ubootfile; " \
374 "if test $? -eq 0; then " \
375 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
376 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
377 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
378 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
379 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
380 "if test $? -ne 0; then " \
381 "echo PROGRAM FAILED; " \
383 "echo PROGRAM SUCCEEDED; " \
386 "echo DOWNLOAD FAILED; " \
389 #define CONFIG_PROG_UBOOT2 \
390 "$download_cmd $loadaddr $ubootfile; " \
391 "if test $? -eq 0; then " \
392 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
393 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
394 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
395 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
396 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
397 "if test $? -ne 0; then " \
398 "echo PROGRAM FAILED; " \
400 "echo PROGRAM SUCCEEDED; " \
403 "echo DOWNLOAD FAILED; " \
406 #define CONFIG_BOOT_OS_NET \
407 "$download_cmd $osaddr $osfile; " \
408 "if test $? -eq 0; then " \
409 "if test -n $fdtaddr; then " \
410 "$download_cmd $fdtaddr $fdtfile; " \
411 "if test $? -eq 0; then " \
412 "bootm $osaddr - $fdtaddr; " \
414 "echo FDT DOWNLOAD FAILED; " \
420 "echo OS DOWNLOAD FAILED; " \
423 #define CONFIG_PROG_OS1 \
424 "$download_cmd $osaddr $osfile; " \
425 "if test $? -eq 0; then " \
426 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
427 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
428 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
429 "if test $? -ne 0; then " \
430 "echo OS PROGRAM FAILED; " \
432 "echo OS PROGRAM SUCCEEDED; " \
435 "echo OS DOWNLOAD FAILED; " \
438 #define CONFIG_PROG_OS2 \
439 "$download_cmd $osaddr $osfile; " \
440 "if test $? -eq 0; then " \
441 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
442 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
443 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
444 "if test $? -ne 0; then " \
445 "echo OS PROGRAM FAILED; " \
447 "echo OS PROGRAM SUCCEEDED; " \
450 "echo OS DOWNLOAD FAILED; " \
453 #define CONFIG_PROG_FDT1 \
454 "$download_cmd $fdtaddr $fdtfile; " \
455 "if test $? -eq 0; then " \
456 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
457 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
458 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
459 "if test $? -ne 0; then " \
460 "echo FDT PROGRAM FAILED; " \
462 "echo FDT PROGRAM SUCCEEDED; " \
465 "echo FDT DOWNLOAD FAILED; " \
468 #define CONFIG_PROG_FDT2 \
469 "$download_cmd $fdtaddr $fdtfile; " \
470 "if test $? -eq 0; then " \
471 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
472 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
473 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
474 "if test $? -ne 0; then " \
475 "echo FDT PROGRAM FAILED; " \
477 "echo FDT PROGRAM SUCCEEDED; " \
480 "echo FDT DOWNLOAD FAILED; " \
483 #define CONFIG_EXTRA_ENV_SETTINGS \
485 "download_cmd=tftp\0" \
486 "console_args=console=ttyS0,115200\0" \
487 "root_args=root=/dev/nfs rw\0" \
488 "misc_args=ip=on\0" \
489 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
490 "bootfile=/home/user/file\0" \
491 "osfile=/home/user/board.uImage\0" \
492 "fdtfile=/home/user/board.dtb\0" \
493 "ubootfile=/home/user/u-boot.bin\0" \
494 "fdtaddr=0x1e00000\0" \
495 "osaddr=0x1000000\0" \
496 "loadaddr=0x1000000\0" \
497 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
498 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
499 "prog_os1="CONFIG_PROG_OS1"\0" \
500 "prog_os2="CONFIG_PROG_OS2"\0" \
501 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
502 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
503 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
504 "bootcmd_flash1=run set_bootargs; " \
505 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
506 "bootcmd_flash2=run set_bootargs; " \
507 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
508 "bootcmd=run bootcmd_flash1\0"
509 #endif /* __CONFIG_H */