git.sur5r.net Git - u-boot/blob - include/configs/xpedite550x.h

   1 /*
   2  * Copyright 2010 Extreme Engineering Solutions, Inc.
   3  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * xpedite550x board configuration file
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17 #define CONFIG_SYS_BOARD_NAME   "XPedite5500"
  18 #define CONFIG_SYS_FORM_PMC_XMC 1
  19 #define CONFIG_PRPMC_PCI_ALIAS  "pci0"  /* Processor PMC interface on pci0 */
  20
  21 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup */
  22 #define CONFIG_PCIE1            1       /* PCIE controller 1 (PEX8112 or XMC) */
  23 #define CONFIG_FSL_PCI_INIT     1       /* Use common FSL init code */
  24 #define CONFIG_PCI_INDIRECT_BRIDGE 1    /* indirect PCI bridge support */
  25 #define CONFIG_SYS_PCI_64BIT    1       /* enable 64-bit PCI resources */
  26 #define CONFIG_FSL_PCIE_RESET   1       /* need PCIe reset errata */
  27
  28 /*
  29  * Multicore config
  30  */
  31 #define CONFIG_MP
  32 #define CONFIG_BPTR_VIRT_ADDR   0xee000000      /* virt boot page address */
  33 #define CONFIG_MPC8xxx_DISABLE_BPTR             /* Don't leave BPTR enabled */
  34
  35 /*
  36  * DDR config
  37  */
  38 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup */
  39 #define CONFIG_DDR_SPD
  40 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  41 #define SPD_EEPROM_ADDRESS                      0x54
  42 #define SPD_EEPROM_OFFSET               0x200   /* OFFSET of SPD in EEPROM */
  43 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  44 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  45 #define CONFIG_DDR_ECC
  46 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  47 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000 /* DDR is system memory*/
  48 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  49 #define CONFIG_VERY_BIG_RAM
  50
  51 #ifndef __ASSEMBLY__
  52 extern unsigned long get_board_sys_clk(unsigned long dummy);
  53 extern unsigned long get_board_ddr_clk(unsigned long dummy);
  54 #endif
  55
  56 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /* sysclk for MPC85xx */
  57 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk(0) /* ddrclk for MPC85xx */
  58
  59 /*
  60  * These can be toggled for performance analysis, otherwise use default.
  61  */
  62 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  63 #define CONFIG_BTB                      /* toggle branch predition */
  64 #define CONFIG_ENABLE_36BIT_PHYS        1
  65
  66 #define CONFIG_SYS_CCSRBAR              0xef000000
  67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  68
  69 /*
  70  * Diagnostics
  71  */
  72 #define CONFIG_SYS_MEMTEST_START        0x10000000
  73 #define CONFIG_SYS_MEMTEST_END          0x20000000
  74 #define CONFIG_POST                     (CONFIG_SYS_POST_MEMORY | \
  75                                          CONFIG_SYS_POST_I2C)
  76 #define I2C_ADDR_LIST                   {CONFIG_SYS_I2C_EEPROM_ADDR,    \
  77                                          CONFIG_SYS_I2C_LM75_ADDR,      \
  78                                          CONFIG_SYS_I2C_LM90_ADDR,      \
  79                                          CONFIG_SYS_I2C_PCA953X_ADDR0,  \
  80                                          CONFIG_SYS_I2C_PCA953X_ADDR2,  \
  81                                          CONFIG_SYS_I2C_PCA953X_ADDR3,  \
  82                                          CONFIG_SYS_I2C_RTC_ADDR}
  83
  84 /*
  85  * Memory map
  86  * 0x0000_0000 0x7fff_ffff      DDR                     2G Cacheable
  87  * 0x8000_0000 0xbfff_ffff      PCIe1 Mem               1G non-cacheable
  88  * 0xe000_0000 0xe7ff_ffff      SRAM/SSRAM/L1 Cache     128M non-cacheable
  89  * 0xe800_0000 0xe87f_ffff      PCIe1 IO                8M non-cacheable
  90  * 0xee00_0000 0xee00_ffff      Boot page translation   4K non-cacheable
  91  * 0xef00_0000 0xef0f_ffff      CCSR/IMMR               1M non-cacheable
  92  * 0xef80_0000 0xef8f_ffff      NAND Flash              1M non-cacheable
  93  * 0xf000_0000 0xf7ff_ffff      NOR Flash 2             128M non-cacheable
  94  * 0xf800_0000 0xffff_ffff      NOR Flash 1             128M non-cacheable
  95  */
  96
  97 #define CONFIG_SYS_LBC_LCRR     (LCRR_CLKDIV_8 | LCRR_EADC_3)
  98
  99 /*
 100  * NAND flash configuration
 101  */
 102 #define CONFIG_SYS_NAND_BASE            0xef800000
 103 #define CONFIG_SYS_NAND_BASE2           0xef840000 /* Unused at this time */
 104 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND_BASE, \
 105                                          CONFIG_SYS_NAND_BASE2}
 106 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 107 #define CONFIG_NAND_FSL_ELBC
 108
 109 /*
 110  * NOR flash configuration
 111  */
 112 #define CONFIG_SYS_FLASH_BASE           0xf8000000
 113 #define CONFIG_SYS_FLASH_BASE2          0xf0000000
 114 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
 115 #define CONFIG_SYS_MAX_FLASH_BANKS      2               /* number of banks */
 116 #define CONFIG_SYS_MAX_FLASH_SECT       1024            /* sectors per device */
 117 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000           /* Flash Erase Timeout (ms) */
 118 #define CONFIG_SYS_FLASH_WRITE_TOUT     500             /* Flash Write Timeout (ms) */
 119 #define CONFIG_FLASH_CFI_DRIVER
 120 #define CONFIG_SYS_FLASH_CFI
 121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 122 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST       { {0xfff40000, 0xc0000}, \
 123                                                   {0xf7f40000, 0xc0000} }
 124 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 125
 126 /*
 127  * Chip select configuration
 128  */
 129 /* NOR Flash 0 on CS0 */
 130 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE  | \
 131                                  BR_PS_16               | \
 132                                  BR_V)
 133 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_128MB            | \
 134                                  OR_GPCM_CSNT           | \
 135                                  OR_GPCM_XACS           | \
 136                                  OR_GPCM_ACS_DIV2       | \
 137                                  OR_GPCM_SCY_8          | \
 138                                  OR_GPCM_TRLX           | \
 139                                  OR_GPCM_EHTR           | \
 140                                  OR_GPCM_EAD)
 141
 142 /* NOR Flash 1 on CS1 */
 143 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_FLASH_BASE2 | \
 144                                  BR_PS_16               | \
 145                                  BR_V)
 146 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 147
 148 /* NAND flash on CS2 */
 149 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_NAND_BASE   | \
 150                                  (2<<BR_DECC_SHIFT)     | \
 151                                  BR_PS_8                | \
 152                                  BR_MS_FCM              | \
 153                                  BR_V)
 154
 155 /* NAND flash on CS2 */
 156 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256KB    | \
 157                                  OR_FCM_PGS     | \
 158                                  OR_FCM_CSCT    | \
 159                                  OR_FCM_CST     | \
 160                                  OR_FCM_CHT     | \
 161                                  OR_FCM_SCY_1   | \
 162                                  OR_FCM_TRLX    | \
 163                                  OR_FCM_EHTR)
 164
 165 /* NAND flash on CS3 */
 166 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_NAND_BASE2  | \
 167                                  (2<<BR_DECC_SHIFT)     | \
 168                                  BR_PS_8                | \
 169                                  BR_MS_FCM              | \
 170                                  BR_V)
 171 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 172
 173 /*
 174  * Use L1 as initial stack
 175  */
 176 #define CONFIG_SYS_INIT_RAM_LOCK        1
 177 #define CONFIG_SYS_INIT_RAM_ADDR        0xe0000000
 178 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 179
 180 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 181 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 182
 183 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 KB for Mon */
 184 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 185
 186 /*
 187  * Serial Port
 188  */
 189 #define CONFIG_SYS_NS16550_SERIAL
 190 #define CONFIG_SYS_NS16550_REG_SIZE     1
 191 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 192 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 193 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 194 #define CONFIG_SYS_BAUDRATE_TABLE       \
 195         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 196 #define CONFIG_LOADS_ECHO               1       /* echo on for serial download */
 197 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 198
 199
 200 /*
 201  * I2C
 202  */
 203 #define CONFIG_SYS_I2C
 204 #define CONFIG_SYS_I2C_FSL
 205 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 206 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 207 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 208 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 209 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 210 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 211
 212 /* I2C DS7505 temperature sensor */
 213 #define CONFIG_SYS_I2C_LM75_ADDR        0x48
 214
 215 /* I2C ADT7461 temperature sensor */
 216 #define CONFIG_SYS_I2C_LM90_ADDR        0x4C
 217
 218 /* I2C EEPROM - AT24C128B */
 219 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x54
 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 221 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6       /* 64 byte pages */
 222 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* take up to 10 msec */
 223
 224 /* I2C RTC */
 225 #define CONFIG_RTC_M41T11               1
 226 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 227 #define CONFIG_SYS_M41T11_BASE_YEAR     2000
 228
 229 /* GPIO */
 230 #define CONFIG_PCA953X
 231 #define CONFIG_SYS_I2C_PCA953X_ADDR0    0x18
 232 #define CONFIG_SYS_I2C_PCA953X_ADDR1    0x1c
 233 #define CONFIG_SYS_I2C_PCA953X_ADDR2    0x1e
 234 #define CONFIG_SYS_I2C_PCA953X_ADDR3    0x1f
 235 #define CONFIG_SYS_I2C_PCA953X_ADDR     CONFIG_SYS_I2C_PCA953X_ADDR0
 236
 237 /*
 238  * GPIO pin definitions, PU = pulled high, PD = pulled low
 239  */
 240 /* PCA9557 @ 0x18*/
 241 #define CONFIG_SYS_PCA953X_C0_SER0_EN           0x01 /* PU; UART0 enable (1: enabled) */
 242 #define CONFIG_SYS_PCA953X_C0_SER0_MODE         0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
 243 #define CONFIG_SYS_PCA953X_C0_SER1_EN           0x04 /* PU; UART1 enable (1: enabled) */
 244 #define CONFIG_SYS_PCA953X_C0_SER1_MODE         0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
 245 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS     0x10 /* PU; Boot flash CS select */
 246 #define CONFIG_SYS_PCA953X_NVM_WP               0x20 /* PU; Write protection (0: disabled, 1: enabled) */
 247
 248 /* PCA9557 @ 0x1e*/
 249 #define CONFIG_SYS_PCA953X_XMC_GA0              0x01 /* PU; */
 250 #define CONFIG_SYS_PCA953X_XMC_GA1              0x02 /* PU; */
 251 #define CONFIG_SYS_PCA953X_XMC_GA2              0x04 /* PU; */
 252 #define CONFIG_SYS_PCA953X_XMC_WAKE             0x10 /* PU; */
 253 #define CONFIG_SYS_PCA953X_XMC_BIST             0x20 /* Enable XMC BIST */
 254 #define CONFIG_SYS_PCA953X_PMC_EREADY           0x40 /* PU; PMC PCI eready */
 255 #define CONFIG_SYS_PCA953X_PMC_MONARCH          0x80 /* PMC monarch mode enable */
 256
 257 /* PCA9557 @ 0x1f */
 258 #define CONFIG_SYS_PCA953X_MC_GPIO0             0x01 /* PU; */
 259 #define CONFIG_SYS_PCA953X_MC_GPIO1             0x02 /* PU; */
 260 #define CONFIG_SYS_PCA953X_MC_GPIO2             0x04 /* PU; */
 261 #define CONFIG_SYS_PCA953X_MC_GPIO3             0x08 /* PU; */
 262 #define CONFIG_SYS_PCA953X_MC_GPIO4             0x10 /* PU; */
 263 #define CONFIG_SYS_PCA953X_MC_GPIO5             0x20 /* PU; */
 264 #define CONFIG_SYS_PCA953X_MC_GPIO6             0x40 /* PU; */
 265 #define CONFIG_SYS_PCA953X_MC_GPIO7             0x80 /* PU; */
 266
 267 /*
 268  * General PCI
 269  * Memory space is mapped 1-1, but I/O space must start from 0.
 270  */
 271
 272 /* controller 1 - PEX8112 or XMC, depending on build option */
 273 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 274 #define CONFIG_SYS_PCIE1_MEM_PHYS       CONFIG_SYS_PCIE1_MEM_BUS
 275 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x40000000      /* 1G */
 276 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 277 #define CONFIG_SYS_PCIE1_IO_PHYS        0xe8000000
 278 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000      /* 8M */
 279
 280 /*
 281  * Networking options
 282  */
 283 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 284 #define CONFIG_TSEC_TBI
 285 #define CONFIG_MII              1       /* MII PHY management */
 286 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 287 #define CONFIG_ETHPRIME         "eTSEC2"
 288
 289 /*
 290  * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
 291  * 1000mbps SGMII link
 292  */
 293 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 294                 TBICR_PHY_RESET \
 295                 | TBICR_FULL_DUPLEX \
 296                 | TBICR_SPEED1_SET \
 297                 )
 298
 299 #define CONFIG_TSEC1            1
 300 #define CONFIG_TSEC1_NAME       "eTSEC1"
 301 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 302 #define TSEC1_PHY_ADDR          1
 303 #define TSEC1_PHYIDX            0
 304 #define CONFIG_HAS_ETH0
 305
 306 #define CONFIG_TSEC2            1
 307 #define CONFIG_TSEC2_NAME       "eTSEC2"
 308 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 309 #define TSEC2_PHY_ADDR          2
 310 #define TSEC2_PHYIDX            0
 311 #define CONFIG_HAS_ETH1
 312
 313 #define CONFIG_TSEC3            1
 314 #define CONFIG_TSEC3_NAME       "eTSEC3"
 315 #define TSEC3_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 316 #define TSEC3_PHY_ADDR          3
 317 #define TSEC3_PHYIDX            0
 318 #define CONFIG_HAS_ETH2
 319
 320 /*
 321  * USB
 322  */
 323 #define CONFIG_USB_EHCI_FSL
 324 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 325
 326 /*
 327  * Miscellaneous configurable options
 328  */
 329 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 330 #define CONFIG_LOADADDR         0x1000000       /* default location for tftp and bootm */
 331 #define CONFIG_PREBOOT                          /* enable preboot variable */
 332 #define CONFIG_INTEGRITY                        /* support booting INTEGRITY OS */
 333
 334 /*
 335  * For booting Linux, the board info and command line data
 336  * have to be in the first 16 MB of memory, since this is
 337  * the maximum mapped by the Linux kernel during initialization.
 338  */
 339 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)      /* Initial Memory map for Linux*/
 340 #define CONFIG_SYS_BOOTM_LEN    (16 << 20)      /* Increase max gunzip size */
 341
 342 /*
 343  * Environment Configuration
 344  */
 345 #define CONFIG_ENV_SECT_SIZE    0x20000         /* 128k (one sector) for env */
 346 #define CONFIG_ENV_SIZE         0x8000
 347 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
 348
 349 /*
 350  * Flash memory map:
 351  * fff80000 - ffffffff     Pri U-Boot (512 KB)
 352  * fff40000 - fff7ffff     Pri U-Boot Environment (256 KB)
 353  * fff00000 - fff3ffff     Pri FDT (256KB)
 354  * fef00000 - ffefffff     Pri OS image (16MB)
 355  * f8000000 - feefffff     Pri OS Use/Filesystem (111MB)
 356  *
 357  * f7f80000 - f7ffffff     Sec U-Boot (512 KB)
 358  * f7f40000 - f7f7ffff     Sec U-Boot Environment (256 KB)
 359  * f7f00000 - f7f3ffff     Sec FDT (256KB)
 360  * f6f00000 - f7efffff     Sec OS image (16MB)
 361  * f0000000 - f6efffff     Sec OS Use/Filesystem (111MB)
 362  */
 363 #define CONFIG_UBOOT1_ENV_ADDR  __stringify(0xfff80000)
 364 #define CONFIG_UBOOT2_ENV_ADDR  __stringify(0xf7f80000)
 365 #define CONFIG_FDT1_ENV_ADDR    __stringify(0xfff00000)
 366 #define CONFIG_FDT2_ENV_ADDR    __stringify(0xf7f00000)
 367 #define CONFIG_OS1_ENV_ADDR     __stringify(0xfef00000)
 368 #define CONFIG_OS2_ENV_ADDR     __stringify(0xf6f00000)
 369
 370 #define CONFIG_PROG_UBOOT1                                              \
 371         "$download_cmd $loadaddr $ubootfile; "                          \
 372         "if test $? -eq 0; then "                                       \
 373                 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; "         \
 374                 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; "               \
 375                 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; "       \
 376                 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; "          \
 377                 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; "      \
 378                 "if test $? -ne 0; then "                               \
 379                         "echo PROGRAM FAILED; "                         \
 380                 "else; "                                                \
 381                         "echo PROGRAM SUCCEEDED; "                      \
 382                 "fi; "                                                  \
 383         "else; "                                                        \
 384                 "echo DOWNLOAD FAILED; "                                \
 385         "fi;"
 386
 387 #define CONFIG_PROG_UBOOT2                                              \
 388         "$download_cmd $loadaddr $ubootfile; "                          \
 389         "if test $? -eq 0; then "                                       \
 390                 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; "         \
 391                 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; "               \
 392                 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; "       \
 393                 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; "          \
 394                 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; "      \
 395                 "if test $? -ne 0; then "                               \
 396                         "echo PROGRAM FAILED; "                         \
 397                 "else; "                                                \
 398                         "echo PROGRAM SUCCEEDED; "                      \
 399                 "fi; "                                                  \
 400         "else; "                                                        \
 401                 "echo DOWNLOAD FAILED; "                                \
 402         "fi;"
 403
 404 #define CONFIG_BOOT_OS_NET                                              \
 405         "$download_cmd $osaddr $osfile; "                               \
 406         "if test $? -eq 0; then "                                       \
 407                 "if test -n $fdtaddr; then "                            \
 408                         "$download_cmd $fdtaddr $fdtfile; "             \
 409                         "if test $? -eq 0; then "                       \
 410                                 "bootm $osaddr - $fdtaddr; "            \
 411                         "else; "                                        \
 412                                 "echo FDT DOWNLOAD FAILED; "            \
 413                         "fi; "                                          \
 414                 "else; "                                                \
 415                         "bootm $osaddr; "                               \
 416                 "fi; "                                                  \
 417         "else; "                                                        \
 418                 "echo OS DOWNLOAD FAILED; "                             \
 419         "fi;"
 420
 421 #define CONFIG_PROG_OS1                                                 \
 422         "$download_cmd $osaddr $osfile; "                               \
 423         "if test $? -eq 0; then "                                       \
 424                 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; "              \
 425                 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "        \
 426                 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; "       \
 427                 "if test $? -ne 0; then "                               \
 428                         "echo OS PROGRAM FAILED; "                      \
 429                 "else; "                                                \
 430                         "echo OS PROGRAM SUCCEEDED; "                   \
 431                 "fi; "                                                  \
 432         "else; "                                                        \
 433                 "echo OS DOWNLOAD FAILED; "                             \
 434         "fi;"
 435
 436 #define CONFIG_PROG_OS2                                                 \
 437         "$download_cmd $osaddr $osfile; "                               \
 438         "if test $? -eq 0; then "                                       \
 439                 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; "              \
 440                 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "        \
 441                 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; "       \
 442                 "if test $? -ne 0; then "                               \
 443                         "echo OS PROGRAM FAILED; "                      \
 444                 "else; "                                                \
 445                         "echo OS PROGRAM SUCCEEDED; "                   \
 446                 "fi; "                                                  \
 447         "else; "                                                        \
 448                 "echo OS DOWNLOAD FAILED; "                             \
 449         "fi;"
 450
 451 #define CONFIG_PROG_FDT1                                                \
 452         "$download_cmd $fdtaddr $fdtfile; "                             \
 453         "if test $? -eq 0; then "                                       \
 454                 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;"              \
 455                 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "      \
 456                 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; "     \
 457                 "if test $? -ne 0; then "                               \
 458                         "echo FDT PROGRAM FAILED; "                     \
 459                 "else; "                                                \
 460                         "echo FDT PROGRAM SUCCEEDED; "                  \
 461                 "fi; "                                                  \
 462         "else; "                                                        \
 463                 "echo FDT DOWNLOAD FAILED; "                            \
 464         "fi;"
 465
 466 #define CONFIG_PROG_FDT2                                                \
 467         "$download_cmd $fdtaddr $fdtfile; "                             \
 468         "if test $? -eq 0; then "                                       \
 469                 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;"              \
 470                 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "      \
 471                 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; "     \
 472                 "if test $? -ne 0; then "                               \
 473                         "echo FDT PROGRAM FAILED; "                     \
 474                 "else; "                                                \
 475                         "echo FDT PROGRAM SUCCEEDED; "                  \
 476                 "fi; "                                                  \
 477         "else; "                                                        \
 478                 "echo FDT DOWNLOAD FAILED; "                            \
 479         "fi;"
 480
 481 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 482         "autoload=yes\0"                                                \
 483         "download_cmd=tftp\0"                                           \
 484         "console_args=console=ttyS0,115200\0"                           \
 485         "root_args=root=/dev/nfs rw\0"                                  \
 486         "misc_args=ip=on\0"                                             \
 487         "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
 488         "bootfile=/home/user/file\0"                                    \
 489         "osfile=/home/user/board.uImage\0"                              \
 490         "fdtfile=/home/user/board.dtb\0"                                \
 491         "ubootfile=/home/user/u-boot.bin\0"                             \
 492         "fdtaddr=0x1e00000\0"                                           \
 493         "osaddr=0x1000000\0"                                            \
 494         "loadaddr=0x1000000\0"                                          \
 495         "prog_uboot1="CONFIG_PROG_UBOOT1"\0"                            \
 496         "prog_uboot2="CONFIG_PROG_UBOOT2"\0"                            \
 497         "prog_os1="CONFIG_PROG_OS1"\0"                                  \
 498         "prog_os2="CONFIG_PROG_OS2"\0"                                  \
 499         "prog_fdt1="CONFIG_PROG_FDT1"\0"                                \
 500         "prog_fdt2="CONFIG_PROG_FDT2"\0"                                \
 501         "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0"          \
 502         "bootcmd_flash1=run set_bootargs; "                             \
 503                 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
 504         "bootcmd_flash2=run set_bootargs; "                             \
 505                 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
 506         "bootcmd=run bootcmd_flash1\0"
 507 #endif  /* __CONFIG_H */