3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * If we are developing, we might want to start armboot from ram
33 * so we MUST NOT initialize critical regs like mem-timing ...
35 #define CONFIG_INIT_CRITICAL
37 /* High Level Configuration Options */
38 #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
39 #define CONFIG_XSENGINE 1
41 #define BOARD_POST_INIT 1
42 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
43 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
45 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
46 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
47 #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
49 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
50 #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
51 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
52 #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
53 #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
54 #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
55 #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
56 #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
57 #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
58 #define CFG_DRAM_BASE 0xa0000000
59 #define CFG_DRAM_SIZE 0x04000000
61 /* FLASH organization */
62 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
63 #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
64 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
65 #define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */
66 #define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */
67 #define CFG_FLASH_BASE PHYS_FLASH_1
68 #define CFG_JFFS2_NUM_BANKS 1
69 #define CFG_JFFS2_FIRST_BANK 0
70 #define CFG_JFFS_CUSTOM_PART 1
72 /* Environment settings */
73 #define CONFIG_ENV_OVERWRITE
74 #define CFG_ENV_IS_IN_FLASH 1
75 #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/
76 #define CFG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */
77 #define CFG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
79 /* timeout values are in ticks */
80 #define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */
81 #define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */
83 /* Size of malloc() pool */
84 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
85 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
87 /* Hardware drivers */
88 #define CONFIG_DRIVER_SMC91111
89 #define CONFIG_SMC91111_BASE 0x04000300
90 #define CONFIG_SMC_USE_32_BIT 1
92 /* select serial console configuration */
93 #define CONFIG_FFUART 1
95 /* allow to overwrite serial and ethaddr */
96 #define CONFIG_BAUDRATE 115200
97 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2)
99 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
100 #include <cmd_confdefs.h>
102 #define CONFIG_BOOTDELAY 3
103 #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
104 #define CONFIG_NETMASK 255.255.255.0
105 #define CONFIG_IPADDR 192.168.1.50
106 #define CONFIG_SERVERIP 192.168.1.2
107 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
108 #define CONFIG_CMDLINE_TAG
110 /* Miscellaneous configurable options */
111 #define CFG_HUSH_PARSER 1
112 #define CFG_PROMPT_HUSH_PS2 "> "
113 #define CFG_LONGHELP /* undef to save memory */
114 #define CFG_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
115 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
116 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
117 #define CFG_MAXARGS 16 /* max number of command args */
118 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
119 #define CFG_MEMTEST_START 0xA0400000 /* memtest works on */
120 #define CFG_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
121 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
122 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
123 #define CFG_MMC_BASE 0xF0000000
124 #define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */
126 /* Stack sizes - The stack sizes are set up in start.S using the settings below */
127 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
128 #ifdef CONFIG_USE_IRQ
129 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
130 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
133 /* GP set register */
134 #define CFG_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
135 #define CFG_GPSR1_VAL 0x00020000 /* nPWE */
136 #define CFG_GPSR2_VAL 0x0000C000 /* CS2, CS3 */
138 /* GP clear register */
139 #define CFG_GPCR0_VAL 0x00000000
140 #define CFG_GPCR1_VAL 0x00000000
141 #define CFG_GPCR2_VAL 0x00000000
143 /* GP direction register */
144 #define CFG_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
145 #define CFG_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
146 #define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
148 /* GP rising edge detect register */
149 #define CFG_GRER0_VAL 0x00000000
150 #define CFG_GRER1_VAL 0x00000000
151 #define CFG_GRER2_VAL 0x00000000
153 /* GP falling edge detect register */
154 #define CFG_GFER0_VAL 0x00000000
155 #define CFG_GFER1_VAL 0x00000000
156 #define CFG_GFER2_VAL 0x00000000
158 /* GP alternate function register */
159 #define CFG_GAFR0_L_VAL 0x80000000 /* CS1 */
160 #define CFG_GAFR0_U_VAL 0x00000010 /* RDY */
161 #define CFG_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
162 #define CFG_GAFR1_U_VAL 0x00000008 /* nPWE */
163 #define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
164 #define CFG_GAFR2_U_VAL 0x00000000
166 #define CFG_PSSR_VAL 0x00000020 /* Power manager sleep status */
167 #define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */
168 #define CFG_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */
169 #define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
171 /* Memory settings */
172 #define CFG_MSC0_VAL 0x25F425F0
174 /* MDCNFG: SDRAM Configuration Register */
175 #define CFG_MDCNFG_VAL 0x000009C9
177 /* MDREFR: SDRAM Refresh Control Register */
178 #define CFG_MDREFR_VAL 0x00018018
180 /* MDMRS: Mode Register Set Configuration Register */
181 #define CFG_MDMRS_VAL 0x00220022
183 #endif /* __CONFIG_H */