2 * Copyright 2017 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
8 #define _ABI_MACH_ASPEED_AST2500_RESET_H_
11 * The values are intentionally layed out as flags in
12 * WDT reset parameter.
15 #define AST_RESET_SOC 0
16 #define AST_RESET_CHIP 1
17 #define AST_RESET_CPU (1 << 1)
18 #define AST_RESET_ARM (1 << 2)
19 #define AST_RESET_COPROC (1 << 3)
20 #define AST_RESET_SDRAM (1 << 4)
21 #define AST_RESET_AHB (1 << 5)
22 #define AST_RESET_I2C (1 << 6)
23 #define AST_RESET_MAC1 (1 << 7)
24 #define AST_RESET_MAC2 (1 << 8)
25 #define AST_RESET_GCRT (1 << 9)
26 #define AST_RESET_USB20 (1 << 10)
27 #define AST_RESET_USB11_HOST (1 << 11)
28 #define AST_RESET_USB11_HID (1 << 12)
29 #define AST_RESET_VIDEO (1 << 13)
30 #define AST_RESET_HAC (1 << 14)
31 #define AST_RESET_LPC (1 << 15)
32 #define AST_RESET_SDIO (1 << 16)
33 #define AST_RESET_MIC (1 << 17)
34 #define AST_RESET_CRT2D (1 << 18)
35 #define AST_RESET_PWM (1 << 19)
36 #define AST_RESET_PECI (1 << 20)
37 #define AST_RESET_JTAG (1 << 21)
38 #define AST_RESET_ADC (1 << 22)
39 #define AST_RESET_GPIO (1 << 23)
40 #define AST_RESET_MCTP (1 << 24)
41 #define AST_RESET_XDMA (1 << 25)
42 #define AST_RESET_SPI (1 << 26)
43 #define AST_RESET_MISC (1 << 27)
45 #endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */