git.sur5r.net Git - u-boot/blob - include/dw_hdmi.h

   1 /*
   2  * Copyright (c) 2015 Google, Inc
   3  * Copyright 2014 Rockchip Inc.
   4  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   5  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _DW_HDMI_H
  11 #define _DW_HDMI_H
  12
  13 #include <edid.h>
  14
  15 #define HDMI_EDID_BLOCK_SIZE            128
  16
  17 /* Identification Registers */
  18 #define HDMI_DESIGN_ID                          0x0000
  19 #define HDMI_REVISION_ID                        0x0001
  20 #define HDMI_PRODUCT_ID0                        0x0002
  21 #define HDMI_PRODUCT_ID1                        0x0003
  22 #define HDMI_CONFIG0_ID                         0x0004
  23 #define HDMI_CONFIG1_ID                         0x0005
  24 #define HDMI_CONFIG2_ID                         0x0006
  25 #define HDMI_CONFIG3_ID                         0x0007
  26
  27 /* Interrupt Registers */
  28 #define HDMI_IH_FC_STAT0                        0x0100
  29 #define HDMI_IH_FC_STAT1                        0x0101
  30 #define HDMI_IH_FC_STAT2                        0x0102
  31 #define HDMI_IH_AS_STAT0                        0x0103
  32 #define HDMI_IH_PHY_STAT0                       0x0104
  33 #define HDMI_IH_I2CM_STAT0                      0x0105
  34 #define HDMI_IH_CEC_STAT0                       0x0106
  35 #define HDMI_IH_VP_STAT0                        0x0107
  36 #define HDMI_IH_I2CMPHY_STAT0                   0x0108
  37 #define HDMI_IH_AHBDMAAUD_STAT0                 0x0109
  38
  39 #define HDMI_IH_MUTE_FC_STAT0                   0x0180
  40 #define HDMI_IH_MUTE_FC_STAT1                   0x0181
  41 #define HDMI_IH_MUTE_FC_STAT2                   0x0182
  42 #define HDMI_IH_MUTE_AS_STAT0                   0x0183
  43 #define HDMI_IH_MUTE_PHY_STAT0                  0x0184
  44 #define HDMI_IH_MUTE_I2CM_STAT0                 0x0185
  45 #define HDMI_IH_MUTE_CEC_STAT0                  0x0186
  46 #define HDMI_IH_MUTE_VP_STAT0                   0x0187
  47 #define HDMI_IH_MUTE_I2CMPHY_STAT0              0x0188
  48 #define HDMI_IH_MUTE_AHBDMAAUD_STAT0            0x0189
  49 #define HDMI_IH_MUTE                            0x01FF
  50
  51 /* Video Sample Registers */
  52 #define HDMI_TX_INVID0                          0x0200
  53 #define HDMI_TX_INSTUFFING                      0x0201
  54 #define HDMI_TX_GYDATA0                         0x0202
  55 #define HDMI_TX_GYDATA1                         0x0203
  56 #define HDMI_TX_RCRDATA0                        0x0204
  57 #define HDMI_TX_RCRDATA1                        0x0205
  58 #define HDMI_TX_BCBDATA0                        0x0206
  59 #define HDMI_TX_BCBDATA1                        0x0207
  60
  61 /* Video Packetizer Registers */
  62 #define HDMI_VP_STATUS                          0x0800
  63 #define HDMI_VP_PR_CD                           0x0801
  64 #define HDMI_VP_STUFF                           0x0802
  65 #define HDMI_VP_REMAP                           0x0803
  66 #define HDMI_VP_CONF                            0x0804
  67 #define HDMI_VP_STAT                            0x0805
  68 #define HDMI_VP_INT                             0x0806
  69 #define HDMI_VP_MASK                            0x0807
  70 #define HDMI_VP_POL                             0x0808
  71
  72 /* Frame Composer Registers */
  73 #define HDMI_FC_INVIDCONF                       0x1000
  74 #define HDMI_FC_INHACTV0                        0x1001
  75 #define HDMI_FC_INHACTV1                        0x1002
  76 #define HDMI_FC_INHBLANK0                       0x1003
  77 #define HDMI_FC_INHBLANK1                       0x1004
  78 #define HDMI_FC_INVACTV0                        0x1005
  79 #define HDMI_FC_INVACTV1                        0x1006
  80 #define HDMI_FC_INVBLANK                        0x1007
  81 #define HDMI_FC_HSYNCINDELAY0                   0x1008
  82 #define HDMI_FC_HSYNCINDELAY1                   0x1009
  83 #define HDMI_FC_HSYNCINWIDTH0                   0x100A
  84 #define HDMI_FC_HSYNCINWIDTH1                   0x100B
  85 #define HDMI_FC_VSYNCINDELAY                    0x100C
  86 #define HDMI_FC_VSYNCINWIDTH                    0x100D
  87 #define HDMI_FC_INFREQ0                         0x100E
  88 #define HDMI_FC_INFREQ1                         0x100F
  89 #define HDMI_FC_INFREQ2                         0x1010
  90 #define HDMI_FC_CTRLDUR                         0x1011
  91 #define HDMI_FC_EXCTRLDUR                       0x1012
  92 #define HDMI_FC_EXCTRLSPAC                      0x1013
  93 #define HDMI_FC_CH0PREAM                        0x1014
  94 #define HDMI_FC_CH1PREAM                        0x1015
  95 #define HDMI_FC_CH2PREAM                        0x1016
  96 #define HDMI_FC_AVICONF3                        0x1017
  97 #define HDMI_FC_GCP                             0x1018
  98 #define HDMI_FC_AVICONF0                        0x1019
  99 #define HDMI_FC_AVICONF1                        0x101A
 100 #define HDMI_FC_AVICONF2                        0x101B
 101 #define HDMI_FC_AVIVID                          0x101C
 102 #define HDMI_FC_AVIETB0                         0x101D
 103 #define HDMI_FC_AVIETB1                         0x101E
 104 #define HDMI_FC_AVISBB0                         0x101F
 105 #define HDMI_FC_AVISBB1                         0x1020
 106 #define HDMI_FC_AVIELB0                         0x1021
 107 #define HDMI_FC_AVIELB1                         0x1022
 108 #define HDMI_FC_AVISRB0                         0x1023
 109 #define HDMI_FC_AVISRB1                         0x1024
 110 #define HDMI_FC_AUDICONF0                       0x1025
 111 #define HDMI_FC_AUDICONF1                       0x1026
 112 #define HDMI_FC_AUDICONF2                       0x1027
 113 #define HDMI_FC_AUDICONF3                       0x1028
 114 #define HDMI_FC_VSDIEEEID0                      0x1029
 115 #define HDMI_FC_VSDSIZE                         0x102A
 116
 117 /* HDMI Source PHY Registers */
 118 #define HDMI_PHY_CONF0                          0x3000
 119 #define HDMI_PHY_TST0                           0x3001
 120 #define HDMI_PHY_TST1                           0x3002
 121 #define HDMI_PHY_TST2                           0x3003
 122 #define HDMI_PHY_STAT0                          0x3004
 123 #define HDMI_PHY_INT0                           0x3005
 124 #define HDMI_PHY_MASK0                          0x3006
 125 #define HDMI_PHY_POL0                           0x3007
 126
 127 /* HDMI Master PHY Registers */
 128 #define HDMI_PHY_I2CM_SLAVE_ADDR                0x3020
 129 #define HDMI_PHY_I2CM_ADDRESS_ADDR              0x3021
 130 #define HDMI_PHY_I2CM_DATAO_1_ADDR              0x3022
 131 #define HDMI_PHY_I2CM_DATAO_0_ADDR              0x3023
 132 #define HDMI_PHY_I2CM_DATAI_1_ADDR              0x3024
 133 #define HDMI_PHY_I2CM_DATAI_0_ADDR              0x3025
 134 #define HDMI_PHY_I2CM_OPERATION_ADDR            0x3026
 135 #define HDMI_PHY_I2CM_INT_ADDR                  0x3027
 136 #define HDMI_PHY_I2CM_CTLINT_ADDR               0x3028
 137 #define HDMI_PHY_I2CM_DIV_ADDR                  0x3029
 138 #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR             0x302a
 139 #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR        0x302b
 140 #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR        0x302c
 141 #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR        0x302d
 142 #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR        0x302e
 143 #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR        0x302f
 144 #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR        0x3030
 145 #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR        0x3031
 146 #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR        0x3032
 147
 148 /* Audio Sampler Registers */
 149 #define HDMI_AUD_CONF0                          0x3100
 150 #define HDMI_AUD_CONF1                          0x3101
 151 #define HDMI_AUD_INT                            0x3102
 152 #define HDMI_AUD_CONF2                          0x3103
 153 #define HDMI_AUD_INT1                           0x3104
 154 #define HDMI_AUD_N1                             0x3200
 155 #define HDMI_AUD_N2                             0x3201
 156 #define HDMI_AUD_N3                             0x3202
 157 #define HDMI_AUD_CTS1                           0x3203
 158 #define HDMI_AUD_CTS2                           0x3204
 159 #define HDMI_AUD_CTS3                           0x3205
 160 #define HDMI_AUD_INPUTCLKFS                     0x3206
 161 #define HDMI_AUD_SPDIFINT                       0x3302
 162 #define HDMI_AUD_CONF0_HBR                      0x3400
 163 #define HDMI_AUD_HBR_STATUS                     0x3401
 164 #define HDMI_AUD_HBR_INT                        0x3402
 165 #define HDMI_AUD_HBR_POL                        0x3403
 166 #define HDMI_AUD_HBR_MASK                       0x3404
 167
 168 /* Main Controller Registers */
 169 #define HDMI_MC_SFRDIV                          0x4000
 170 #define HDMI_MC_CLKDIS                          0x4001
 171 #define HDMI_MC_SWRSTZ                          0x4002
 172 #define HDMI_MC_OPCTRL                          0x4003
 173 #define HDMI_MC_FLOWCTRL                        0x4004
 174 #define HDMI_MC_PHYRSTZ                         0x4005
 175 #define HDMI_MC_LOCKONCLOCK                     0x4006
 176 #define HDMI_MC_HEACPHY_RST                     0x4007
 177
 178 /* I2C Master Registers (E-DDC) */
 179 #define HDMI_I2CM_SLAVE                         0x7E00
 180 #define HDMI_I2CM_ADDRESS                       0x7E01
 181 #define HDMI_I2CM_DATAO                         0x7E02
 182 #define HDMI_I2CM_DATAI                         0x7E03
 183 #define HDMI_I2CM_OPERATION                     0x7E04
 184 #define HDMI_I2CM_INT                           0x7E05
 185 #define HDMI_I2CM_CTLINT                        0x7E06
 186 #define HDMI_I2CM_DIV                           0x7E07
 187 #define HDMI_I2CM_SEGADDR                       0x7E08
 188 #define HDMI_I2CM_SOFTRSTZ                      0x7E09
 189 #define HDMI_I2CM_SEGPTR                        0x7E0A
 190 #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR            0x7E0B
 191 #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR            0x7E0C
 192 #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR            0x7E0D
 193 #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR            0x7E0E
 194 #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR            0x7E0F
 195 #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
 196 #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
 197 #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
 198 #define HDMI_I2CM_BUF0                          0x7E20
 199
 200 enum {
 201         /* HDMI PHY registers define */
 202         PHY_OPMODE_PLLCFG = 0x06,
 203         PHY_CKCALCTRL = 0x05,
 204         PHY_CKSYMTXCTRL = 0x09,
 205         PHY_VLEVCTRL = 0x0e,
 206         PHY_PLLCURRCTRL = 0x10,
 207         PHY_PLLPHBYCTRL = 0x13,
 208         PHY_PLLGMPCTRL = 0x15,
 209         PHY_PLLCLKBISTPHASE = 0x17,
 210         PHY_TXTERM = 0x19,
 211
 212         /* ih_phy_stat0 field values */
 213         HDMI_IH_PHY_STAT0_HPD = 0x1,
 214
 215         /* ih_mute field values */
 216         HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
 217         HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
 218
 219         /* tx_invid0 field values */
 220         HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
 221         HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
 222         HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
 223
 224         /* tx_instuffing field values */
 225         HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
 226         HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
 227         HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
 228
 229         /* vp_pr_cd field values */
 230         HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
 231         HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
 232         HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
 233         HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
 234
 235         /* vp_stuff field values */
 236         HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
 237         HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
 238         HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
 239         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
 240         HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
 241         HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
 242         HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
 243         HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
 244
 245         /* vp_conf field values */
 246         HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
 247         HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
 248         HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
 249         HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
 250         HDMI_VP_CONF_PR_EN_MASK = 0x10,
 251         HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
 252         HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
 253         HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
 254         HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
 255         HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
 256         HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
 257         HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
 258
 259         /* vp_remap field values */
 260         HDMI_VP_REMAP_YCC422_16BIT = 0x0,
 261
 262         /* fc_invidconf field values */
 263         HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
 264         HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
 265         HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
 266         HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
 267         HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
 268         HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
 269         HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
 270         HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
 271         HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
 272         HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
 273         HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
 274         HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
 275         HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
 276         HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
 277         HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
 278         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
 279         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
 280         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
 281         HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
 282         HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
 283         HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
 284
 285
 286         /* fc_aviconf0-fc_aviconf3 field values */
 287         HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
 288         HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
 289         HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
 290         HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
 291         HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
 292         HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
 293         HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
 294         HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
 295         HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
 296         HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
 297         HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
 298         HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
 299         HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
 300         HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
 301         HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
 302         HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
 303
 304         HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
 305         HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
 306         HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
 307         HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
 308         HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
 309         HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
 310         HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
 311         HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
 312         HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
 313         HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
 314         HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
 315         HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
 316         HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
 317         HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
 318
 319         HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
 320         HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
 321         HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
 322         HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
 323         HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
 324         HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
 325         HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
 326         HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
 327         HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
 328         HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
 329         HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
 330         HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
 331         HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
 332         HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
 333         HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
 334         HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
 335         HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
 336         HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
 337
 338         HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
 339         HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
 340         HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
 341         HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
 342         HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
 343         HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
 344         HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
 345         HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
 346
 347         /* fc_gcp field values*/
 348         HDMI_FC_GCP_SET_AVMUTE = 0x02,
 349         HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
 350
 351         /* phy_conf0 field values */
 352         HDMI_PHY_CONF0_PDZ_MASK = 0x80,
 353         HDMI_PHY_CONF0_PDZ_OFFSET = 7,
 354         HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
 355         HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
 356         HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
 357         HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
 358         HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
 359         HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
 360         HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
 361         HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
 362         HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
 363         HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
 364         HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
 365         HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
 366
 367         /* phy_tst0 field values */
 368         HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
 369         HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
 370
 371         /* phy_stat0 field values */
 372         HDMI_PHY_HPD = 0x02,
 373         HDMI_PHY_TX_PHY_LOCK = 0x01,
 374
 375         /* phy_i2cm_slave_addr field values */
 376         HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
 377
 378         /* phy_i2cm_operation_addr field values */
 379         HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
 380
 381         /* hdmi_phy_i2cm_int_addr */
 382         HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
 383
 384         /* hdmi_phy_i2cm_ctlint_addr */
 385         HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
 386         HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
 387
 388         /* aud_conf0 field values */
 389         HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
 390         HDMI_AUD_CONF0_I2S_SELECT = 0x20,
 391         HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
 392         HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
 393         HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
 394         HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
 395
 396         /* aud_conf0 field values */
 397         HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
 398         HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
 399
 400         /* aud_n3 field values */
 401         HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
 402         HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
 403
 404         /* aud_cts3 field values */
 405         HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
 406         HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
 407         HDMI_AUD_CTS3_N_SHIFT_1 = 0,
 408         HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
 409         HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
 410         HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
 411         HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
 412         HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
 413         HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
 414         HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
 415
 416         /* aud_inputclkfs filed values */
 417         HDMI_AUD_INPUTCLKFS_128 = 0x0,
 418
 419         /* mc_clkdis field values */
 420         HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
 421         HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
 422         HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
 423
 424         /* mc_swrstz field values */
 425         HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
 426         HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
 427
 428         /* mc_flowctrl field values */
 429         HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
 430         HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
 431
 432         /* mc_phyrstz field values */
 433         HDMI_MC_PHYRSTZ_ASSERT = 0x0,
 434         HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
 435
 436         /* mc_heacphy_rst field values */
 437         HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
 438
 439         /* i2cm filed values */
 440         HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
 441         HDMI_I2CM_SEGADDR_DDC = 0x30,
 442         HDMI_I2CM_OP_RD8_EXT = 0x2,
 443         HDMI_I2CM_OP_RD8 = 0x1,
 444         HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
 445         HDMI_I2CM_DIV_FAST_MODE = 0x8,
 446         HDMI_I2CM_DIV_STD_MODE = 0x0,
 447         HDMI_I2CM_SOFTRSTZ_MASK = 0x1,
 448 };
 449
 450 struct hdmi_mpll_config {
 451         u64 mpixelclock;
 452         /* Mode of Operation and PLL Dividers Control Register */
 453         u32 cpce;
 454         /* PLL Gmp Control Register */
 455         u32 gmp;
 456         /* PLL Current Control Register */
 457         u32 curr;
 458 };
 459
 460 struct hdmi_phy_config {
 461         u64 mpixelclock;
 462         u32 sym_ctr;    /* clock symbol and transmitter control */
 463         u32 term;       /* transmission termination value */
 464         u32 vlev_ctr;   /* voltage level control */
 465 };
 466
 467 struct dw_hdmi {
 468         ulong ioaddr;
 469         const struct hdmi_mpll_config *mpll_cfg;
 470         const struct hdmi_phy_config *phy_cfg;
 471         u8 i2c_clk_high;
 472         u8 i2c_clk_low;
 473         u8 reg_io_width;
 474
 475         int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
 476 };
 477
 478 int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
 479 int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
 480 void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
 481
 482 int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
 483 int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
 484 void dw_hdmi_init(struct dw_hdmi *hdmi);
 485
 486 #endif