1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
5 * Copyright (C) 2010 Andes Technology Corporation
6 * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
7 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
13 /* AHB Control Registers */
14 struct ftpci100_ahbc {
15 unsigned int iosize; /* 0x00 - I/O Space Size Signal */
16 unsigned int prot; /* 0x04 - AHB Protection */
17 unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
18 unsigned int conf; /* 0x28 - PCI Configuration */
19 unsigned int data; /* 0x2c - PCI Configuration DATA */
23 * FTPCI100_IOSIZE_REG's constant definitions
25 #define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
28 * PCI Configuration Register
30 #define PCI_INT_MASK 0x4c
31 #define PCI_MEM_BASE_SIZE1 0x50
32 #define PCI_MEM_BASE_SIZE2 0x54
33 #define PCI_MEM_BASE_SIZE3 0x58
36 * PCI_INT_MASK's bit definitions
38 #define PCI_INTA_ENABLE (1 << 22)
39 #define PCI_INTB_ENABLE (1 << 23)
40 #define PCI_INTC_ENABLE (1 << 24)
41 #define PCI_INTD_ENABLE (1 << 25)
44 * PCI_MEM_BASE_SIZE1's constant definitions
46 #define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */
48 #define FTPCI100_MAX_FUNCTIONS 20
49 #define PCI_IRQ_LINES 4
51 #define MAX_BUS_NUM 256
52 #define MAX_DEV_NUM 32
55 #define PCI_MAX_BAR_PER_FUNC 6
60 #define FTPCI100_MEM_SIZE(x) (ffs(x) << 24)
62 /* This definition is used by pci_ftpci_init() */
63 #define FTPCI100_BRIDGE_VENDORID 0x159b
64 #define FTPCI100_BRIDGE_DEVICEID 0x4321
66 void pci_ftpci_init(void);
75 unsigned int dev; /* device */
78 unsigned short v_id; /* vendor id */
79 unsigned short d_id; /* device id */
80 struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];