2 * Watchdog driver for the FTWDT010 Watch Dog Driver
4 * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
5 * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
6 * Based on SoftDog driver by Alan Cox <alan@redhat.com>
8 * Copyright (C) 2011 Andes Technology Corporation
9 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * 27/11/2004 Initial release, Faraday.
26 * 12/01/2011 Port to u-boot, Macpaul Lin.
33 unsigned int wdcounter; /* Counter Reg - 0x00 */
34 unsigned int wdload; /* Counter Auto Reload Reg - 0x04 */
35 unsigned int wdrestart; /* Counter Restart Reg - 0x08 */
36 unsigned int wdcr; /* Control Reg - 0x0c */
37 unsigned int wdstatus; /* Status Reg - 0x10 */
38 unsigned int wdclear; /* Timer Clear - 0x14 */
39 unsigned int wdintrlen; /* Interrupt Length - 0x18 */
43 * WDLOAD - Counter Auto Reload Register
44 * The Auto Reload Register is set to 0x03EF1480 (66Mhz) by default.
45 * Which means in a 66MHz system, the period of Watch Dog timer reset is
48 #define FTWDT010_WDLOAD(x) ((x) & 0xffffffff)
51 * WDRESTART - Watch Dog Timer Counter Restart Register
52 * If writing 0x5AB9 to WDRESTART register, Watch Dog timer will
53 * automatically reload WDLOAD to WDCOUNTER and restart counting.
55 #define FTWDT010_WDRESTART_MAGIC 0x5AB9
57 /* WDCR - Watch Dog Timer Control Register */
58 #define FTWDT010_WDCR_ENABLE (1 << 0)
59 #define FTWDT010_WDCR_RST (1 << 1)
60 #define FTWDT010_WDCR_INTR (1 << 2)
61 /* FTWDT010_WDCR_EXT bit: Watch Dog Timer External Signal Enable */
62 #define FTWDT010_WDCR_EXT (1 << 3)
63 /* FTWDT010_WDCR_CLOCK bit: Clock Source: 0: PCLK, 1: EXTCLK.
64 * The clock source PCLK cannot be gated when system sleeps, even if
65 * WDCLOCK bit is turned on.
67 * Faraday's Watch Dog timer can be driven by an external clock. The
68 * programmer just needs to write one to WdCR[WdClock] bit.
70 * Note: There is a limitation between EXTCLK and PCLK:
71 * EXTCLK cycle time / PCLK cycle time > 2.
72 * If the system does not need an external clock,
73 * just keep WdCR[WdClock] bit in its default value.
75 #define FTWDT010_WDCR_CLOCK (1 << 4)
78 * WDSTATUS - Watch Dog Timer Status Register
79 * This bit is set when the counter reaches Zero
81 #define FTWDT010_WDSTATUS(x) ((x) & 0x1)
84 * WDCLEAR - Watch Dog Timer Clear Register
85 * Writing one to this register will clear WDSTATUS.
87 #define FTWDT010_WDCLEAR (1 << 0)
90 * WDINTRLEN - Watch Dog Timer Interrupt Length
91 * This register controls the duration length of wd_rst, wd_intr and wd_ext.
92 * The default value is 0xFF.
94 #define FTWDT010_WDINTRLEN(x) ((x) & 0xff)
97 * Variable timeout should be set in ms.
98 * (CONFIG_SYS_CLK_FREQ/1000) equals 1 ms.
99 * WDLOAD = timeout * TIMEOUT_FACTOR.
101 #define FTWDT010_TIMEOUT_FACTOR (CONFIG_SYS_CLK_FREQ / 1000) /* 1 ms */
103 void ftwdt010_wdt_reset(void);
104 void ftwdt010_wdt_disable(void);
106 #endif /* __FTWDT010_H */