3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/types.h> /* for ulong typedef */
13 #ifndef CONFIG_MAX_FPGA_DEVICES
14 #define CONFIG_MAX_FPGA_DEVICES 5
17 /* fpga_xxxx function return value definitions */
18 #define FPGA_SUCCESS 0
21 /* device numbers must be non-negative */
22 #define FPGA_INVALID_DEVICE -1
24 /* root data type defintions */
25 typedef enum { /* typedef fpga_type */
26 fpga_min_type, /* range check value */
27 fpga_xilinx, /* Xilinx Family) */
28 fpga_altera, /* unimplemented */
29 fpga_lattice, /* Lattice family */
30 fpga_undefined /* invalid range check value */
31 } fpga_type; /* end, typedef fpga_type */
33 typedef struct { /* typedef fpga_desc */
34 fpga_type devtype; /* switch value to select sub-functions */
35 void *devdesc; /* real device descriptor */
36 } fpga_desc; /* end, typedef fpga_desc */
38 typedef struct { /* typedef fpga_desc */
39 unsigned int blocksize;
52 /* root function definitions */
54 int fpga_add(fpga_type devtype, void *desc);
56 const fpga_desc *const fpga_get_desc(int devnum);
57 int fpga_is_partial_data(int devnum, size_t img_len);
58 int fpga_load(int devnum, const void *buf, size_t bsize,
59 bitstream_type bstype);
60 int fpga_fsload(int devnum, const void *buf, size_t size,
61 fpga_fs_info *fpga_fsinfo);
62 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
63 bitstream_type bstype);
64 int fpga_dump(int devnum, const void *buf, size_t bsize);
65 int fpga_info(int devnum);
66 const fpga_desc *const fpga_validate(int devnum, const void *buf,
67 size_t bsize, char *fn);