1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7 #include <linux/types.h> /* for ulong typedef */
12 #ifndef CONFIG_MAX_FPGA_DEVICES
13 #define CONFIG_MAX_FPGA_DEVICES 5
16 /* fpga_xxxx function return value definitions */
17 #define FPGA_SUCCESS 0
20 /* device numbers must be non-negative */
21 #define FPGA_INVALID_DEVICE -1
23 /* root data type defintions */
24 typedef enum { /* typedef fpga_type */
25 fpga_min_type, /* range check value */
26 fpga_xilinx, /* Xilinx Family) */
27 fpga_altera, /* unimplemented */
28 fpga_lattice, /* Lattice family */
29 fpga_undefined /* invalid range check value */
30 } fpga_type; /* end, typedef fpga_type */
32 typedef struct { /* typedef fpga_desc */
33 fpga_type devtype; /* switch value to select sub-functions */
34 void *devdesc; /* real device descriptor */
35 } fpga_desc; /* end, typedef fpga_desc */
37 typedef struct { /* typedef fpga_desc */
38 unsigned int blocksize;
51 /* root function definitions */
53 int fpga_add(fpga_type devtype, void *desc);
55 const fpga_desc *const fpga_get_desc(int devnum);
56 int fpga_is_partial_data(int devnum, size_t img_len);
57 int fpga_load(int devnum, const void *buf, size_t bsize,
58 bitstream_type bstype);
59 int fpga_fsload(int devnum, const void *buf, size_t size,
60 fpga_fs_info *fpga_fsinfo);
61 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
62 bitstream_type bstype);
63 int fpga_dump(int devnum, const void *buf, size_t bsize);
64 int fpga_info(int devnum);
65 const fpga_desc *const fpga_validate(int devnum, const void *buf,
66 size_t bsize, char *fn);