git.sur5r.net Git - u-boot/blob - include/fsl_ddr.h

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #ifndef FSL_DDR_MAIN_H
  10 #define FSL_DDR_MAIN_H
  11
  12 #include <fsl_ddrc_version.h>
  13 #include <fsl_ddr_sdram.h>
  14 #include <fsl_ddr_dimm_params.h>
  15
  16 #include <common_timing_params.h>
  17
  18 #ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
  19 /* All controllers are for main memory */
  20 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       CONFIG_NUM_DDR_CONTROLLERS
  21 #endif
  22
  23 #ifdef CONFIG_SYS_FSL_DDR_LE
  24 #define ddr_in32(a)     in_le32(a)
  25 #define ddr_out32(a, v) out_le32(a, v)
  26 #define ddr_setbits32(a, v)     setbits_le32(a, v)
  27 #define ddr_clrbits32(a, v)     clrbits_le32(a, v)
  28 #define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
  29 #else
  30 #define ddr_in32(a)     in_be32(a)
  31 #define ddr_out32(a, v) out_be32(a, v)
  32 #define ddr_setbits32(a, v)     setbits_be32(a, v)
  33 #define ddr_clrbits32(a, v)     clrbits_be32(a, v)
  34 #define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
  35 #endif
  36
  37 #define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR
  38
  39 u32 fsl_ddr_get_version(void);
  40
  41 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
  42 /*
  43  * Bind the main DDR setup driver's generic names
  44  * to this specific DDR technology.
  45  */
  46 static __inline__ int
  47 compute_dimm_parameters(const generic_spd_eeprom_t *spd,
  48                         dimm_params_t *pdimm,
  49                         unsigned int dimm_number)
  50 {
  51         return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
  52 }
  53 #endif
  54
  55 /*
  56  * Data Structures
  57  *
  58  * All data structures have to be on the stack
  59  */
  60 #define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
  61 #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
  62
  63 typedef struct {
  64         generic_spd_eeprom_t
  65            spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  66         struct dimm_params_s
  67            dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
  68         memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
  69         common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
  70         fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
  71         unsigned int first_ctrl;
  72         unsigned int num_ctrls;
  73         unsigned long long mem_base;
  74         unsigned int dimm_slots_per_ctrl;
  75         int (*board_need_mem_reset)(void);
  76         void (*board_mem_reset)(void);
  77         void (*board_mem_de_reset)(void);
  78 } fsl_ddr_info_t;
  79
  80 /* Compute steps */
  81 #define STEP_GET_SPD                 (1 << 0)
  82 #define STEP_COMPUTE_DIMM_PARMS      (1 << 1)
  83 #define STEP_COMPUTE_COMMON_PARMS    (1 << 2)
  84 #define STEP_GATHER_OPTS             (1 << 3)
  85 #define STEP_ASSIGN_ADDRESSES        (1 << 4)
  86 #define STEP_COMPUTE_REGS            (1 << 5)
  87 #define STEP_PROGRAM_REGS            (1 << 6)
  88 #define STEP_ALL                     0xFFF
  89
  90 unsigned long long
  91 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
  92                                        unsigned int size_only);
  93 const char *step_to_string(unsigned int step);
  94
  95 unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
  96                                fsl_ddr_cfg_regs_t *ddr,
  97                                const common_timing_params_t *common_dimm,
  98                                const dimm_params_t *dimm_parameters,
  99                                unsigned int dbw_capacity_adjust,
 100                                unsigned int size_only);
 101 unsigned int compute_lowest_common_dimm_parameters(
 102                                 const dimm_params_t *dimm_params,
 103                                 common_timing_params_t *outpdimm,
 104                                 unsigned int number_of_dimms);
 105 unsigned int populate_memctl_options(int all_dimms_registered,
 106                                 memctl_options_t *popts,
 107                                 dimm_params_t *pdimm,
 108                                 unsigned int ctrl_num);
 109 void check_interleaving_options(fsl_ddr_info_t *pinfo);
 110
 111 unsigned int mclk_to_picos(unsigned int mclk);
 112 unsigned int get_memory_clk_period_ps(void);
 113 unsigned int picos_to_mclk(unsigned int picos);
 114 void fsl_ddr_set_lawbar(
 115                 const common_timing_params_t *memctl_common_params,
 116                 unsigned int memctl_interleaved,
 117                 unsigned int ctrl_num);
 118
 119 int fsl_ddr_interactive_env_var_exists(void);
 120 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
 121 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 122                      unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
 123
 124 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 125 unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
 126 void board_add_ram_info(int use_default);
 127
 128 /* processor specific function */
 129 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 130                                    unsigned int ctrl_num, int step);
 131
 132 /* board specific function */
 133 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 134                         unsigned int controller_number,
 135                         unsigned int dimm_number);
 136 #endif