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1 /*
2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8
9 #ifndef FSL_DDR_MEMCTL_H
10 #define FSL_DDR_MEMCTL_H
11
12 /*
13  * Pick a basic DDR Technology.
14  */
15 #include <ddr_spd.h>
16 #include <fsl_ddrc_version.h>
17
18 #define SDRAM_TYPE_DDR1         2
19 #define SDRAM_TYPE_DDR2         3
20 #define SDRAM_TYPE_LPDDR1       6
21 #define SDRAM_TYPE_DDR3         7
22 #define SDRAM_TYPE_DDR4         5
23
24 #define DDR_BL4         4       /* burst length 4 */
25 #define DDR_BC4         DDR_BL4 /* burst chop for ddr3 */
26 #define DDR_OTF         6       /* on-the-fly BC4 and BL8 */
27 #define DDR_BL8         8       /* burst length 8 */
28
29 #define DDR3_RTT_OFF            0
30 #define DDR3_RTT_60_OHM         1 /* RTT_Nom = RZQ/4 */
31 #define DDR3_RTT_120_OHM        2 /* RTT_Nom = RZQ/2 */
32 #define DDR3_RTT_40_OHM         3 /* RTT_Nom = RZQ/6 */
33 #define DDR3_RTT_20_OHM         4 /* RTT_Nom = RZQ/12 */
34 #define DDR3_RTT_30_OHM         5 /* RTT_Nom = RZQ/8 */
35
36 #define DDR2_RTT_OFF            0
37 #define DDR2_RTT_75_OHM         1
38 #define DDR2_RTT_150_OHM        2
39 #define DDR2_RTT_50_OHM         3
40
41 #if defined(CONFIG_SYS_FSL_DDR1)
42 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR        (1)
43 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;
44 #ifndef CONFIG_FSL_SDRAM_TYPE
45 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR1
46 #endif
47 #elif defined(CONFIG_SYS_FSL_DDR2)
48 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR        (3)
49 typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
50 #ifndef CONFIG_FSL_SDRAM_TYPE
51 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR2
52 #endif
53 #elif defined(CONFIG_SYS_FSL_DDR3)
54 typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
55 #ifndef CONFIG_FSL_SDRAM_TYPE
56 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR3
57 #endif
58 #elif defined(CONFIG_SYS_FSL_DDR4)
59 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR        (3)     /* FIXME */
60 typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
61 #ifndef CONFIG_FSL_SDRAM_TYPE
62 #define CONFIG_FSL_SDRAM_TYPE   SDRAM_TYPE_DDR4
63 #endif
64 #endif  /* #if defined(CONFIG_SYS_FSL_DDR1) */
65
66 #define FSL_DDR_ODT_NEVER               0x0
67 #define FSL_DDR_ODT_CS                  0x1
68 #define FSL_DDR_ODT_ALL_OTHER_CS        0x2
69 #define FSL_DDR_ODT_OTHER_DIMM          0x3
70 #define FSL_DDR_ODT_ALL                 0x4
71 #define FSL_DDR_ODT_SAME_DIMM           0x5
72 #define FSL_DDR_ODT_CS_AND_OTHER_DIMM   0x6
73 #define FSL_DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
74
75 /* define bank(chip select) interleaving mode */
76 #define FSL_DDR_CS0_CS1                 0x40
77 #define FSL_DDR_CS2_CS3                 0x20
78 #define FSL_DDR_CS0_CS1_AND_CS2_CS3     (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
79 #define FSL_DDR_CS0_CS1_CS2_CS3         (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
80
81 /* define memory controller interleaving mode */
82 #define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
83 #define FSL_DDR_PAGE_INTERLEAVING       0x1
84 #define FSL_DDR_BANK_INTERLEAVING       0x2
85 #define FSL_DDR_SUPERBANK_INTERLEAVING  0x3
86 #define FSL_DDR_256B_INTERLEAVING       0x8
87 #define FSL_DDR_3WAY_1KB_INTERLEAVING   0xA
88 #define FSL_DDR_3WAY_4KB_INTERLEAVING   0xC
89 #define FSL_DDR_3WAY_8KB_INTERLEAVING   0xD
90 /* placeholder for 4-way interleaving */
91 #define FSL_DDR_4WAY_1KB_INTERLEAVING   0x1A
92 #define FSL_DDR_4WAY_4KB_INTERLEAVING   0x1C
93 #define FSL_DDR_4WAY_8KB_INTERLEAVING   0x1D
94
95 #define SDRAM_CS_CONFIG_EN              0x80000000
96
97 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
98  */
99 #define SDRAM_CFG_MEM_EN                0x80000000
100 #define SDRAM_CFG_SREN                  0x40000000
101 #define SDRAM_CFG_ECC_EN                0x20000000
102 #define SDRAM_CFG_RD_EN                 0x10000000
103 #define SDRAM_CFG_SDRAM_TYPE_DDR1       0x02000000
104 #define SDRAM_CFG_SDRAM_TYPE_DDR2       0x03000000
105 #define SDRAM_CFG_SDRAM_TYPE_MASK       0x07000000
106 #define SDRAM_CFG_SDRAM_TYPE_SHIFT      24
107 #define SDRAM_CFG_DYN_PWR               0x00200000
108 #define SDRAM_CFG_DBW_MASK              0x00180000
109 #define SDRAM_CFG_DBW_SHIFT             19
110 #define SDRAM_CFG_32_BE                 0x00080000
111 #define SDRAM_CFG_16_BE                 0x00100000
112 #define SDRAM_CFG_8_BE                  0x00040000
113 #define SDRAM_CFG_NCAP                  0x00020000
114 #define SDRAM_CFG_2T_EN                 0x00008000
115 #define SDRAM_CFG_BI                    0x00000001
116
117 #define SDRAM_CFG2_FRC_SR               0x80000000
118 #define SDRAM_CFG2_D_INIT               0x00000010
119 #define SDRAM_CFG2_ODT_CFG_MASK         0x00600000
120 #define SDRAM_CFG2_ODT_NEVER            0
121 #define SDRAM_CFG2_ODT_ONLY_WRITE       1
122 #define SDRAM_CFG2_ODT_ONLY_READ        2
123 #define SDRAM_CFG2_ODT_ALWAYS           3
124
125 #define TIMING_CFG_2_CPO_MASK   0x0F800000
126
127 #if defined(CONFIG_SYS_FSL_DDR_VER) && \
128         (CONFIG_SYS_FSL_DDR_VER > FSL_DDR_VER_4_4)
129 #define RD_TO_PRE_MASK          0xf
130 #define RD_TO_PRE_SHIFT         13
131 #define WR_DATA_DELAY_MASK      0xf
132 #define WR_DATA_DELAY_SHIFT     9
133 #else
134 #define RD_TO_PRE_MASK          0x7
135 #define RD_TO_PRE_SHIFT         13
136 #define WR_DATA_DELAY_MASK      0x7
137 #define WR_DATA_DELAY_SHIFT     10
138 #endif
139
140 /* DDR_MD_CNTL */
141 #define MD_CNTL_MD_EN           0x80000000
142 #define MD_CNTL_CS_SEL_CS0      0x00000000
143 #define MD_CNTL_CS_SEL_CS1      0x10000000
144 #define MD_CNTL_CS_SEL_CS2      0x20000000
145 #define MD_CNTL_CS_SEL_CS3      0x30000000
146 #define MD_CNTL_CS_SEL_CS0_CS1  0x40000000
147 #define MD_CNTL_CS_SEL_CS2_CS3  0x50000000
148 #define MD_CNTL_MD_SEL_MR       0x00000000
149 #define MD_CNTL_MD_SEL_EMR      0x01000000
150 #define MD_CNTL_MD_SEL_EMR2     0x02000000
151 #define MD_CNTL_MD_SEL_EMR3     0x03000000
152 #define MD_CNTL_SET_REF         0x00800000
153 #define MD_CNTL_SET_PRE         0x00400000
154 #define MD_CNTL_CKE_CNTL_LOW    0x00100000
155 #define MD_CNTL_CKE_CNTL_HIGH   0x00200000
156 #define MD_CNTL_WRCW            0x00080000
157 #define MD_CNTL_MD_VALUE(x)     (x & 0x0000FFFF)
158
159 /* DDR_CDR1 */
160 #define DDR_CDR1_DHC_EN 0x80000000
161 #define DDR_CDR1_ODT_SHIFT      17
162 #define DDR_CDR1_ODT_MASK       0x6
163 #define DDR_CDR2_ODT_MASK       0x1
164 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
165 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
166 #define DDR_CDR2_VREF_OVRD(x)   (0x00008080 | ((((x) - 37) & 0x3F) << 8))
167 #define DDR_CDR2_VREF_TRAIN_EN  0x00000080
168
169 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
170         (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
171 #ifdef CONFIG_SYS_FSL_DDR3L
172 #define DDR_CDR_ODT_OFF         0x0
173 #define DDR_CDR_ODT_120ohm      0x1
174 #define DDR_CDR_ODT_200ohm      0x2
175 #define DDR_CDR_ODT_75ohm       0x3
176 #define DDR_CDR_ODT_60ohm       0x5
177 #define DDR_CDR_ODT_46ohm       0x7
178 #elif defined(CONFIG_SYS_FSL_DDR4)
179 #define DDR_CDR_ODT_OFF         0x0
180 #define DDR_CDR_ODT_100ohm      0x1
181 #define DDR_CDR_ODT_120OHM      0x2
182 #define DDR_CDR_ODT_80ohm       0x3
183 #define DDR_CDR_ODT_60ohm       0x4
184 #define DDR_CDR_ODT_40ohm       0x5
185 #define DDR_CDR_ODT_50ohm       0x6
186 #define DDR_CDR_ODT_30ohm       0x7
187 #else
188 #define DDR_CDR_ODT_OFF         0x0
189 #define DDR_CDR_ODT_120ohm      0x1
190 #define DDR_CDR_ODT_180ohm      0x2
191 #define DDR_CDR_ODT_75ohm       0x3
192 #define DDR_CDR_ODT_110ohm      0x4
193 #define DDR_CDR_ODT_60hm        0x5
194 #define DDR_CDR_ODT_70ohm       0x6
195 #define DDR_CDR_ODT_47ohm       0x7
196 #endif /* DDR3L */
197 #else
198 #define DDR_CDR_ODT_75ohm       0x0
199 #define DDR_CDR_ODT_55ohm       0x1
200 #define DDR_CDR_ODT_60ohm       0x2
201 #define DDR_CDR_ODT_50ohm       0x3
202 #define DDR_CDR_ODT_150ohm      0x4
203 #define DDR_CDR_ODT_43ohm       0x5
204 #define DDR_CDR_ODT_120ohm      0x6
205 #endif
206
207 #define DDR_INIT_ADDR_EXT_UIA   (1 << 31)
208
209 /* Record of register values computed */
210 typedef struct fsl_ddr_cfg_regs_s {
211         struct {
212                 unsigned int bnds;
213                 unsigned int config;
214                 unsigned int config_2;
215         } cs[CONFIG_CHIP_SELECTS_PER_CTRL];
216         unsigned int timing_cfg_3;
217         unsigned int timing_cfg_0;
218         unsigned int timing_cfg_1;
219         unsigned int timing_cfg_2;
220         unsigned int ddr_sdram_cfg;
221         unsigned int ddr_sdram_cfg_2;
222         unsigned int ddr_sdram_cfg_3;
223         unsigned int ddr_sdram_mode;
224         unsigned int ddr_sdram_mode_2;
225         unsigned int ddr_sdram_mode_3;
226         unsigned int ddr_sdram_mode_4;
227         unsigned int ddr_sdram_mode_5;
228         unsigned int ddr_sdram_mode_6;
229         unsigned int ddr_sdram_mode_7;
230         unsigned int ddr_sdram_mode_8;
231         unsigned int ddr_sdram_mode_9;
232         unsigned int ddr_sdram_mode_10;
233         unsigned int ddr_sdram_mode_11;
234         unsigned int ddr_sdram_mode_12;
235         unsigned int ddr_sdram_mode_13;
236         unsigned int ddr_sdram_mode_14;
237         unsigned int ddr_sdram_mode_15;
238         unsigned int ddr_sdram_mode_16;
239         unsigned int ddr_sdram_md_cntl;
240         unsigned int ddr_sdram_interval;
241         unsigned int ddr_data_init;
242         unsigned int ddr_sdram_clk_cntl;
243         unsigned int ddr_init_addr;
244         unsigned int ddr_init_ext_addr;
245         unsigned int timing_cfg_4;
246         unsigned int timing_cfg_5;
247         unsigned int timing_cfg_6;
248         unsigned int timing_cfg_7;
249         unsigned int timing_cfg_8;
250         unsigned int timing_cfg_9;
251         unsigned int ddr_zq_cntl;
252         unsigned int ddr_wrlvl_cntl;
253         unsigned int ddr_wrlvl_cntl_2;
254         unsigned int ddr_wrlvl_cntl_3;
255         unsigned int ddr_sr_cntr;
256         unsigned int ddr_sdram_rcw_1;
257         unsigned int ddr_sdram_rcw_2;
258         unsigned int ddr_sdram_rcw_3;
259         unsigned int ddr_sdram_rcw_4;
260         unsigned int ddr_sdram_rcw_5;
261         unsigned int ddr_sdram_rcw_6;
262         unsigned int dq_map_0;
263         unsigned int dq_map_1;
264         unsigned int dq_map_2;
265         unsigned int dq_map_3;
266         unsigned int ddr_eor;
267         unsigned int ddr_cdr1;
268         unsigned int ddr_cdr2;
269         unsigned int err_disable;
270         unsigned int err_int_en;
271         unsigned int debug[32];
272 } fsl_ddr_cfg_regs_t;
273
274 typedef struct memctl_options_partial_s {
275         unsigned int all_dimms_ecc_capable;
276         unsigned int all_dimms_tckmax_ps;
277         unsigned int all_dimms_burst_lengths_bitmask;
278         unsigned int all_dimms_registered;
279         unsigned int all_dimms_unbuffered;
280         /*      unsigned int lowest_common_spd_caslat; */
281         unsigned int all_dimms_minimum_trcd_ps;
282 } memctl_options_partial_t;
283
284 #define DDR_DATA_BUS_WIDTH_64 0
285 #define DDR_DATA_BUS_WIDTH_32 1
286 #define DDR_DATA_BUS_WIDTH_16 2
287 #define DDR_CSWL_CS0    0x04000001
288 /*
289  * Generalized parameters for memory controller configuration,
290  * might be a little specific to the FSL memory controller
291  */
292 typedef struct memctl_options_s {
293         /*
294          * Memory organization parameters
295          *
296          * if DIMM is present in the system
297          * where DIMMs are with respect to chip select
298          * where chip selects are with respect to memory boundaries
299          */
300         unsigned int registered_dimm_en;    /* use registered DIMM support */
301
302         /* Options local to a Chip Select */
303         struct cs_local_opts_s {
304                 unsigned int auto_precharge;
305                 unsigned int odt_rd_cfg;
306                 unsigned int odt_wr_cfg;
307                 unsigned int odt_rtt_norm;
308                 unsigned int odt_rtt_wr;
309         } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
310
311         /* Special configurations for chip select */
312         unsigned int memctl_interleaving;
313         unsigned int memctl_interleaving_mode;
314         unsigned int ba_intlv_ctl;
315         unsigned int addr_hash;
316
317         /* Operational mode parameters */
318         unsigned int ecc_mode;   /* Use ECC? */
319         /* Initialize ECC using memory controller? */
320         unsigned int ecc_init_using_memctl;
321         unsigned int dqs_config;        /* Use DQS? maybe only with DDR2? */
322         /* SREN - self-refresh during sleep */
323         unsigned int self_refresh_in_sleep;
324         unsigned int dynamic_power;     /* DYN_PWR */
325         /* memory data width to use (16-bit, 32-bit, 64-bit) */
326         unsigned int data_bus_width;
327         unsigned int burst_length;      /* BL4, OTF and BL8 */
328         /* On-The-Fly Burst Chop enable */
329         unsigned int otf_burst_chop_en;
330         /* mirrior DIMMs for DDR3 */
331         unsigned int mirrored_dimm;
332         unsigned int quad_rank_present;
333         unsigned int ap_en;     /* address parity enable for RDIMM */
334         unsigned int x4_en;     /* enable x4 devices */
335
336         /* Global Timing Parameters */
337         unsigned int cas_latency_override;
338         unsigned int cas_latency_override_value;
339         unsigned int use_derated_caslat;
340         unsigned int additive_latency_override;
341         unsigned int additive_latency_override_value;
342
343         unsigned int clk_adjust;                /* */
344         unsigned int cpo_override;
345         unsigned int write_data_delay;          /* DQS adjust */
346
347         unsigned int cswl_override;
348         unsigned int wrlvl_override;
349         unsigned int wrlvl_sample;              /* Write leveling */
350         unsigned int wrlvl_start;
351         unsigned int wrlvl_ctl_2;
352         unsigned int wrlvl_ctl_3;
353
354         unsigned int half_strength_driver_enable;
355         unsigned int twot_en;
356         unsigned int threet_en;
357         unsigned int bstopre;
358         unsigned int tfaw_window_four_activates_ps;     /* tFAW --  FOUR_ACT */
359
360         /* Rtt impedance */
361         unsigned int rtt_override;              /* rtt_override enable */
362         unsigned int rtt_override_value;        /* that is Rtt_Nom for DDR3 */
363         unsigned int rtt_wr_override_value;     /* this is Rtt_WR for DDR3 */
364
365         /* Automatic self refresh */
366         unsigned int auto_self_refresh_en;
367         unsigned int sr_it;
368         /* ZQ calibration */
369         unsigned int zq_en;
370         /* Write leveling */
371         unsigned int wrlvl_en;
372         /* RCW override for RDIMM */
373         unsigned int rcw_override;
374         unsigned int rcw_1;
375         unsigned int rcw_2;
376         /* control register 1 */
377         unsigned int ddr_cdr1;
378         unsigned int ddr_cdr2;
379
380         unsigned int trwt_override;
381         unsigned int trwt;                      /* read-to-write turnaround */
382 } memctl_options_t;
383
384 phys_size_t fsl_ddr_sdram(void);
385 phys_size_t fsl_ddr_sdram_size(void);
386 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
387                                 unsigned int first_ctrl,
388                                 unsigned int num_ctrls,
389                                 unsigned int dimm_slots_per_ctrl,
390                                 int (*board_need_reset)(void),
391                                 void (*board_reset)(void),
392                                 void (*board_de_reset)(void));
393 extern int fsl_use_spd(void);
394 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
395                              unsigned int ctrl_num, int step);
396 u32 fsl_ddr_get_intl3r(void);
397 void print_ddr_info(unsigned int start_ctrl);
398
399 static void __board_assert_mem_reset(void)
400 {
401 }
402
403 static void __board_deassert_mem_reset(void)
404 {
405 }
406
407 void board_assert_mem_reset(void)
408         __attribute__((weak, alias("__board_assert_mem_reset")));
409
410 void board_deassert_mem_reset(void)
411         __attribute__((weak, alias("__board_deassert_mem_reset")));
412
413 static int __board_need_mem_reset(void)
414 {
415         return 0;
416 }
417
418 int board_need_mem_reset(void)
419         __attribute__((weak, alias("__board_need_mem_reset")));
420
421 #if defined(CONFIG_DEEP_SLEEP)
422 void board_mem_sleep_setup(void);
423 bool is_warm_boot(void);
424 int fsl_dp_resume(void);
425 #endif
426
427 /*
428  * The 85xx boards have a common prototype for fixed_sdram so put the
429  * declaration here.
430  */
431 #ifdef CONFIG_MPC85xx
432 extern phys_size_t fixed_sdram(void);
433 #endif
434
435 #if defined(CONFIG_DDR_ECC)
436 extern void ddr_enable_ecc(unsigned int dram_size);
437 #endif
438
439
440 typedef struct fixed_ddr_parm{
441         int min_freq;
442         int max_freq;
443         fsl_ddr_cfg_regs_t *ddr_settings;
444 } fixed_ddr_parm_t;
445 #endif