2 * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * TODO: Use same register defs for nand_spl mxc nand driver
28 * and mtd mxc nand driver.
30 * Register map and bit definitions for the Freescale NAND Flash
31 * Controller present in various i.MX devices.
33 * MX31 and MX27 have version 1 which has
34 * 4 512 byte main buffers and
35 * 4 16 byte spare buffers
36 * to support up to 2K byte pagesize nand.
37 * Reading or writing a 2K page requires 4 FDI/FDO cycles.
39 * MX25 has version 1.1 which has
40 * 8 512 byte main buffers and
41 * 8 64 byte spare buffers
42 * to support up to 4K byte pagesize nand.
43 * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
44 * Also some of registers are moved and/or changed meaning as seen below.
46 #if defined(CONFIG_NAND_MXC_V1)
47 #define NAND_MXC_NR_BUFS 4
48 #define NAND_MXC_SPARE_BUF_SIZE 16
49 #define NAND_MXC_REG_OFFSET 0xe00
50 #define NAND_MXC_2K_MULTI_CYCLE 1
51 #elif defined(CONFIG_NAND_MXC_V1_1)
52 #define NAND_MXC_NR_BUFS 8
53 #define NAND_MXC_SPARE_BUF_SIZE 64
54 #define NAND_MXC_REG_OFFSET 0x1e00
56 #error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
60 u8 main_area[NAND_MXC_NR_BUFS][512];
61 u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE];
63 * reserved size is offset of nfc registers
64 * minus total main and spare sizes
66 u8 reserved1[NAND_MXC_REG_OFFSET
67 - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
68 #if defined(CONFIG_NAND_MXC_V1)
75 u16 ecc_status_result;
76 u16 ecc_rslt_main_area;
77 u16 ecc_rslt_spare_area;
79 u16 unlock_start_blk_add;
80 u16 unlock_end_blk_add;
81 u16 nand_flash_wr_pr_st;
82 u16 nand_flash_config1;
83 u16 nand_flash_config2;
84 #elif defined(CONFIG_NAND_MXC_V1_1)
90 u16 ecc_status_result;
91 u16 ecc_status_result2;
95 u16 nand_flash_wr_pr_st;
96 u16 nand_flash_config1;
97 u16 nand_flash_config2;
99 u16 unlock_start_blk_add0;
100 u16 unlock_end_blk_add0;
101 u16 unlock_start_blk_add1;
102 u16 unlock_end_blk_add1;
103 u16 unlock_start_blk_add2;
104 u16 unlock_end_blk_add2;
105 u16 unlock_start_blk_add3;
106 u16 unlock_end_blk_add3;
111 * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command
117 * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address
123 * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input
126 #define NFC_INPUT 0x4
129 * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data
132 #define NFC_OUTPUT 0x8
135 * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID
141 * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read
144 #define NFC_STATUS 0x20
147 * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status
150 #define NFC_INT 0x8000
152 #ifdef CONFIG_NAND_MXC_V1_1
153 #define NFC_4_8N_ECC (1 << 0)
155 #define NFC_SP_EN (1 << 2)
156 #define NFC_ECC_EN (1 << 3)
157 #define NFC_INT_MSK (1 << 4)
158 #define NFC_BIG (1 << 5)
159 #define NFC_RST (1 << 6)
160 #define NFC_CE (1 << 7)
161 #define NFC_ONE_CYCLE (1 << 8)
163 #endif /* __FSL_NFC_H */